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DVCon 2013 Preview – Learn from Other Design and Verification Engineers

Comments(0)Filed under: Industry Insights, DVCon, SystemC, IP-XACT, TLM, Accellera, verification, Functional Verification, Verification IP, VIP, UVM, Debug, Krolikoski, Cadence, formal verification, DVCon 2013, verification planning

The Design and Verification Conference (DVCon 2013) will be held Feb. 25-28 at the Doubletree Hotel in San Jose, California - and this year's program has something of interest for almost every design and verification engineer. The conference offers 12 technical sessions, 10 tutorials, two panels, a keynote, and two days of exhibits. Most of the papers reflect challenges and successes experienced by engineers in their work.

Stan Krolikoski (right) , distinguished engineer at Cadence and EDA standards veteran, is the DVCon 2013 general chair. "DVCon 2013 focuses on presenting practical information that designers and functional verification engineers can immediately use in their current  work," he said. "This focus can be seen in the four Monday tutorials that cover the IEEE and Accellera Systems Initiative standards IP-XACT, SystemC, UPF, and UVM from a use and deployment point of view. Similarly, the technical program contains multiple case study and deployment sessions."

As Krolikoski points out on the DVCon web site, this is the tenth anniversary of DVCon under its current name, and the 25th anniversary if you go back to the first meeting of the VHDL International User's Forum in 1988 (that event later merged with the International Verilog HDL Conference into "HDLCon" and finally "DVCon.") One new feature this year is the availability of WI-FI access in all conference rooms. Another new feature is expanded exhibit hours, now set for 3:30-6:00 pm Tuesday and Wednesday, Feb. 26-27.

Here is a listing of events at DVCon 2013, followed by a list of Cadence co-authored papers. For further information about Cadence activities at DVCon, click here.


Tutorial 1: Lessons from the Trenches: Migrating Legacy Verification Environments to UVM (8:30 am - 12:00 pm). Doulos, Intel, Qualcomm, Texas Instruments, Analog Devices, Freescale, Intel

Tutorial 2: Increasing Productivity with SystemC in Complex System Design and Verification (9:00 am - 12:00 pm). Doulos, Intel, Cadence, Mentor, Synopsys

Sponsored Luncheon: Town Hall Lunch with the Accellera Systems Initiative (12:00 pm - 1:15 pm). Open Q&A on Accellera standards - read about last year's session here.

Tutorial 3: Low Power Design, Verification, and Implementation with IEEE 1801 UPF (1:30 pm - 4:30 pm). ARM, Broadcom, Cadence, Mentor, Synopsys

Tutorial 4: User Experiences at the Forefront of Mixed-Signal Design and Verification (1:30 pm - 4:30 pm). AMD, Maxim, Fraunhofer IIS, STMicroelectronics, NXP, Designers Guide Consulting, Infineon


DVCon 2013 Opening Session (8:30 am - 9:00 am)

Session 1: Deployment of UCIS (9:00 am - 10:30 am)
Session 2: Case Studies - 1 (9:00 am - 10:30 am)
Session 3: Formal and Semi-Formal Techniques (9:00 am - 10:30 am)

Poster Session 1: (10:30 am - 11:30 am)

Sponsored Lunch: The Changing Landscape in Functional Verification (11:30 am - 12:45 pm) Mentor Graphics

Session 4: Verification Process and Resource Management (1:00pm - 3:00pm)
Session 5: System-on-Chip Design and Verification (1:00pm - 3:00pm)
Session 6: Verification Techniques (1:00pm - 3:00pm)

Keynote: Accelerating EDA Innovation Through SoC Design Methodology Convergence (3:30 pm - 4:30 pm). Wally Rhines, Mentor Graphics CEO


Panel: Where Does Design End and Verification Begin? (8:30 am - 10:00 am) Real Intent, ARM, Mentor, Intel, Gary Smith

Session 7: ESL and/or TLM (10:30 am - 12:00 pm)
Session 8: Hardcore UVM - 1 (10:30 am - 12:00 pm)
Session 9: Mixed-Signal Power Aware Design and Verification (10:30 am - 12:00 pm)

Sponsored Lunch: Expert Panel - Best Practices in Verification Planning (12:00 pm - 1:15 pm). Sponsored by Cadence. Panelists from Verilab, Cadence, Paradigm Works, Maxim, Oski Technology.

Session 10: Case Studies - 2 (1:30 pm - 3:00 pm)
Session 11: Hardcore UVM - 2 (1:30 pm - 3:00 pm)
Session 12: PotPourri (1:30 pm - 3:00 pm)

Panel: The Road to 1M Design Starts (3:30 - 4:30 pm) Moderated by J.L. Gray of Verilab, panelists not listed as of this writing


Tutorial 5: Fast Track Your UVM Debug Productivity with Simulation and Acceleration (8:30 am - 12:00 pm). Sponsored by Cadence.

Tutorial 6: We've Got You Covered: Practical Advice for Achieving Coverage Closure (8:30 am - 12:00 pm). Sponsored by Mentor Graphics.

Tutorial 7: Higher-Level Verification IP (VIP) Capabilities Accelerate SoC Verification (8:30 am -- 12:00 pm). Sponsored by Synopsys.

Sponsored Luncheon: Industry Leaders Verify with Synopsys (12:00 pm - 1:30 pm)

Tutorial 8: Achieving Visibility into the Functional Verification Process Using Assertion Synthesis (1:30 pm - 5:00 pm). Sponsored by Atrenta.

Tutorial 9: A Formal Approach to Low Power Verification (1:30 pm - 5:00 pm). Sponsored by Jasper.

Tutorial 10: Pre-Simulation Verification for RTL Sign-off (1:30 pm - 5:00 pm). Sponsored by Real Intent.


Besides the sponsored luncheon "expert panel" and Tutorial 5 mentioned above, where else will you find Cadence at DVCon? The following paper sessions have Cadence authors or co-authors (see times given above):

Session 2.1: Overcoming AXI Asynchronous Bridge Verification Challenges with AXI Assertion-Based Verification IP (ABVIP) and Formal Datapath Scoreboards. Cadence, ST-Ericsson

Session 3.1: How to Kill 4 Birds with 1 Stone: In a Highly Configurable Design Using Formal to Validate Legal Configurations, Find Design Bugs, and Improve Testbench and Software Specifications. Cadence, Xilinx

Session 4.2: Best Practices in Verification Planning. Cadence, Freescale

Session 9.3: MS-SoC Best Practices - Advanced Modeling and Verification Techniques for First-Pass Success. Maxim, Cadence

Session 12.1: Real Number Modeling: An Effective Approach for Modeling of Digital Behavior and Signal Interactions in Analog Blocks. Cadence, Cirrus Logic

For further information and registration, see the DVCon 2013 web site. Rates go up Jan. 29. See you at DVCon!

Richard Goering



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