A 3D multi-gate transistor called the FinFET promises tremendous power and performance advantages at 16nm and 14nm process nodes (and was adopted at 22nm by Intel) -- but nobody can use FinFETs without an accurate compact model. Fortunately, the BSIM-CMG model available from the University of California at Berkeley provides just that, and Cadence and other industry partners helped develop it.
The term FinFET was coined by Prof. Chenming Hu and other U.C. Berkeley researchers to describe a new type of multi-gate, non-planar transistor. In a FinFET, the FET gate wraps around three sides of the transistor's elevated channel, or "fin," forming conducting channels on three sides of the vertical fin structure. This new 3D structure requires a new model, and that's why the BSIM Group of the U.C. Berkeley Device Group developed BSIM-CMG.
The BSIM-CMG model was developed to model the electrical characteristics of multi-gate structures. It considers finite body doping, volume inversion, electro-static potential in the body of multi-gate MOSFETs, electrostatic control from the end-gates, and many other effects. The model is implemented in Verilog-A and has been verified with experimental industrial data.
Different FinFET structures that can be modeled by BSIM-CMG (Source: Navid Paydavosi via Wikimedia Commons)
BSIM-CMG 106.0.0 was officially released March 1, 2012. This was the first standard model for FinFETs. The current release, BSIM-CMG 106.1.0, was released Sept. 11, 2012. A number of "unofficial" releases preceded these two releases. You can download the 106.1.0 release and view a technical manual here.
What are the advantages of BSIM-CMG over BSIM4? A FAQ compiled by the BSIM Group lists these BSIM-CMG features:
- Scalability with FinFET related geometry, including parameters such as HFIN (height of the fin) and NFIN (number of fins).
- Accurate predictions of variability effects in these parameters
- Smoothness of the model and accurate capacitances
- Accurate descriptions of parasitics for FinFET geometry
- Multi-fin, multi-finger demarcation in the model through NFIN
- Accurate capture of quantum effects for thin body
Input from Industry
A model such as BSIM-CMG doesn't only happen in academia. Input from industry is crucial, and the technical manual for the 106.1.0 release includes acknowledgements for (in alphabetical order) Accelicon, Cadence, Freescale, GLOBALFOUNDRIES, IBM, Proplus Solutions, Qualcomm, Silvaco, Synopsys, Texas Instruments, and TSMC. I talked with Jushan Xie, engineering director for the circuit simulation team at Cadence, about the Cadence role in FinFET device model development.
Xie noted that Cadence works with Berkeley on all kinds of models. "Whenever Berkeley has a new model or a new version, they talk to us," he said. "We share our expertise on how to implement the model and improve performance. We work with Berkeley on bug fixing and model improvement."
Xie said that Cadence started working with Berkeley on FinFET device modeling about four years ago, beginning with "research work" before there was much foundry involvement. This work became more intensive within the past three years, and it included early releases up to the latest release. Cadence worked with both U.C. Berkeley and foundries to ensure that the BSIM-CMG model was accurate and had good simulation performance. "We really did a lot of work," Xie said. And the work goes on, with 10nm and 7nm in sight.
So how is the FinFET device model different from planar transistor models? Because the FinFET has a 3D structure, the modeling concept is quite different from planar CMOS, Xie said. Now you have to add several gates together (three for tri-gate) to get the width; consider resistance and capacitance parasitics from fin extensions; and use a surface potential modeling approach that is more physical. One limitation of FinFETs is that continuous transistor sizing is not supported - designers can't change the width or height of a fin. (That's why the HFIN parameter mentioned above is currently treated as a model parameter rather than an instance parameter - fin height is expected to remain constant for a given technology.)
Work has also been ongoing inside of Cadence to ensure that tools support BSIM-CMG FinFET models. Cadence simulation, timing, extraction, and cell characterization tools support the models.
Earlier this month I wrote about a 14nm FinFET test chip tapeout in which ARM, Cadence and Samsung accomplished the digital implementation in about 8 weeks. This kind of success could not have happened without the R&D effort to develop an accurate device model. BSIM-CMG is just one part of a massive, industry-wide R&D effort to enable FinFET technology, an effort that deeply involves Cadence and many of its partners.
Note: Prof. Hu visited Cadence in 2009 and 2011 and gave well-attended technical talks introducing FinFETs. For a detailed review of the 2011 talk, see Steve Leibson's EDA360 Insider blog post.
Related Blog Posts
Cadence, ARM, Samsung 14nm Test Chip - Collaboration Eases FinFET Digital Implementation
ARM TechCon: Inside Story of a 14nm FinFET Tapeout
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TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs
FinFETs, Tri-Gate Transistors Promise Low Power - But Pose Some Design Challenges