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User Video and Presentation: Mixed-Signal Design Using OpenAccess

Comments(0)Filed under: Industry Insights, Virtuoso, Encounter, OpenAccess, Mixed-Signal, mixed signal, floorplanning, parasitics, place and route, Fast SPICE, OA, static timing analysis, UltraSim, full-chip integration, technology summit, Shetty, digital on top, Spansion, OA mixed signal

A distinctive aspect of the Cadence Mixed-Signal Solution is the use of the OpenAccess database to integrate custom/analog (Virtuoso) with digital (Encounter Digital Implementation System) design. Embedded memory provider Spansion has given this methodology a thorough road test, as reported at the 2012 Mixed-Signal Technology Summit. Now you can view a video of this 20-minute presentation and see the slides at the Mixed-Signal Technology Summit proceedings page (Cadence Community log-in required to view proceedings).

The presentation was titled "OA Based Concurrent Mixed Signal Flow." It was authored by Dinraj Shetty, director of CAD and methodology at Spansion, and Joaquin Bartra, senior manager for CAD at Spansion. Shetty started the presentation by talking about interoperability challenges in mixed-signal design.

"We have a big divide between the styles of engineers in today's environment," Shetty said. "Logic designers are talking code. Circuit designers understand resistors and capacitors. Layout designers are looking at polygons and putting this all together." The divide is made worse, he noted, because design is so often done by multiple, geographically-dispersed teams.

What's needed, he said, is a strong version control environment that allows seamless access to data throughout the world. "But unless we have real-time access to this stuff, a lot of these flows will break," Shetty said. "So we need to build an infrastructure with the assumption that designers can access all this data in real time, quickly."

Coming Together

Shetty presented a mixed-signal interoperability environment that includes the following steps on the analog side:

  • Full chip floorplanning and custom pre-route
  • Block level circuit design
  • Post place and route integration
  • Full chip analog simulation with parasitic
  • Physical verification

The following tasks are accomplished on the digital side:

  • RTL design and full chip integration
  • Physical synthesis
  • Place and route
  • Full chip static timing analysis
  • Logic verification

These tasks need to be brought together in real time, Shetty said. "What you don't want to do is to try and integrate this at the end of the project. You don't want silos where the circuit designers and the logic designers build their pieces, and then you try to slap it all together and hope everything works before you tape out. We did that for years and it was a terrible idea."

"So we moved away from that into an environment where this integration happens live, and it happens throughout the design flow and not just at the end. And OpenAccess is one of the key ingredients to making that happen."

Digital on Top

Shetty went on to describe the design flow that Spansion uses with the industry-standard OpenAccess database. It's a "digital on top" flow, which means the top-level integration is done in Verilog and the schematic is drawn in Virtuoso. All circuit blocks are defined as macros, which are represented in the top-level integration by their own relative data, such as behavioral models or .lib models. Timing is verified using static timing analysis, and functional verification uses the Fast SPICE Ultrasim simulator.

In the OpenAccess design flow, logic designers do the logic design, and analog designers then use Virtuoso to build a full chip schematic. From that schematic, designers can run pre-layout and post-layout simulation. A "constraint database" holds information about signals that are critical to the analog design and need special care, such as shielding. All this information is passed to the Encounter Digital Implementation System, which provides a digital flow including synthesis, extraction, and full chip static timing analysis.

A benefit of the OpenAccess integration, Shetty said, is that designers get to use "real" parasitic data versus "assumed" data. That's because designers can run full-chip simulations with true parasitics early in the design flow. Further, the integration provides fast turnaround time for both analog and digital ECOs, and leverages the custom environment for design cleanup.

In summary, Shetty said, OpenAccess is key to improving Spansion's design throughput. It reduces the need for translation between formats. And thanks to the flow, "analog and digital designers are able to work together and share information fairly seamlessly."

The Spansion video is one of several that are available on the Mixed-Signal Technology Summit proceedings page. Videos and/or slides are also available from Boeing, Micron, Analog Bits, Maxim, and Cadence. Click here for details.

Richard Goering

 

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