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CDNLive! 2012 Proceedings – Over 150 User Presentations on Design and Verification

Comments(0)Filed under: ESL, low power, SoC, digital implementation, Analog, verification, IP, Mixed-Signal, mixed signal, Functional Verification, Logic Design, CDNLive! Silcon Valley, CDNLive!, PCB, CDNlive, Cadence, digital, custom/analog, packaging, system-level design, CDN Live, CDNLive! 2012, user presentations, CDNLive proceedings

A fantastic resource is available for chip and system designers -- proceedings from five of the CDNLive! Conferences held in 2012. By my count this includes over 150 user-authored presentations given at CDNLive! Silicon Valley (March 12-13), CDNLive! EMEA (May 6-8), CDNLive! Taiwan (July 11), CDNLive! India (Oct. 9), and CDNLive! Israel (Oct. 14). Cadence Community members can access any of these presentations here (quick and free registration if you're not a member).

The presentations cover just about every aspect of IC and system design and verification, including custom/analog, functional verification, mixed-signal, low power, front-end design, physical design, PCB and packaging, and more. Here's your chance to learn about the challenges faced by Cadence users and the solutions they've discovered. Meanwhile, mark your calendar for CDNLive Silicon Valley 2013, planned for March 12-13 in Santa Clara, California. You can learn more about this conference, and view a short 2012 "highlights" video, here.

Here's a listing of the user presentations you can access from the CDNLive! 2012 conferences. There's sure to be something of interest for almost any designer.

CDNLive! Silicon Valley 2012 Proceedings

Custom - 7 user presentations

  • Freescale - Layout dependent effect aware design
  • Analog Devices - Circuit Prospector tool
  • Cortina Systems - Early signoff-quality verification
  • STMicroelectronics - 20nm challenges in PDK development
  • Freescale - Evaluation of fluid guard rings
  • Freescale - Minimizing schematic migration with autonomous super symbols
  • Spansion - SKILL tool for power grid optimization

Digital - 7 user presentations

  • Applied Micro -- Conformal Constraint Designer
  • Samsung - In-design DFM using pattern matching
  • Cisco - Early architecture exploration
  • Avago - Floorplan route planning using bus guides
  • Netronome ---Distributed parallel test architecture
  • Texas Instruments - QRC/ETS solutions for 28nm timing signoff
  • Cisco - EDI System interface with IBM ASIC

Functional Verification -- 9 user presentations

  • LSI - Best practices of assertion based verification
  • Cisco - Automating memory wrapper verification
  • LSI - Metric driven verification planning and management
  • Freescale - Concurrent coverage-driven verification
  • IBM - Metric driven verification
  • Marvell - Formal verification of an arbiter
  • Verifysis - Easy writing of SystemVerilog test cases
  • Freescale/Cadence - UVM SDMAM technique for SoC verification
  • Veriest Venture - Module testing vs. full chip verification

High Performance - 3 user presentations

  • ARM - Flow and library validation of 22nm test chip
  • Netronome/Cadence - Clock concurrent optimization reduces power
  • Broadcom - Clock concurrent optimization

Mixed-Signal/Low Power - 7 user presentations

  • Rambus - Low-power, mixed-signal verification using Conformal LP
  • LSI - Real number modeling model development
  • Texas Instruments - Analog/mixed-signal simulation of USB interface
  • NVIDIA - Phase-lock loop noise simulation
  • Texas Instruments - Use model schemes for OSS/IRUN flow
  • Qualcomm - Conformal Low Power
  • Freescale - Low power implementation of Kinetis family

PCB - 2 user presentations

  • Adiva - Why doesn't my board work?
  • Teradyne - Improving IDF geometry definitions

SoC/Design IP - 1 user presentation

  • LeCroy - PCIe post silicon validation

Special Topics - 4 user presentations

  • Integra Design Solutions - Early power rail analysis
  • IGNIS Innovation - Parasitic extraction for display technologies
  • Silicon Labs - Interoperable real number models
  • Renesas - Substrate noise analysis and wide metal extraction

System Verification - 4 user presentations

  • PMC-Sierra/Cadence - Next generation functional verification tools
  • AMD - System level debug with in-circuit emulation
  • Freescale - At-speed waveform generation using Palladium

System/Software/IC Packaging -- 4 user presentations

  • Analog Devices - MCM package design
  • Broadcom - Using co-design to optimize system interconnect paths
  • Bayside Design - Silicon/package/board co-design for multicore chip
  • ARM - Leveraging virtual platforms in subsystem design

CDNLive! EMEA 2012 Proceedings

Custom Design - 7 user presentations

  • Infineon - Detection of FOX parasitic MOS structures
  • Ericsson - Static and dynamic error mechanisms of D/A converters
  • ST-Ericsson - Top level mixed-signal SoC verification
  • NXP - Predictability of parasitics for RF designs
  • Texas Instruments - ADE XL for signoff simulations
  • ATEEDA - Analog BIST generation
  • Missing Link Electronics - Verilog-AMS verification of ADC IP cores

Digital Implementation - 9 user presentations

  • Texas Instruments - Automation of switch insertion and power networks
  • ARM - Flow and library validation on a 22nm test chip
  • Texas Instruments - Multi voltage domain, multi Vt physical implementation
  • Renesas - Power calculation from early estimation to silicon correlation
  • IMEC - Implementation of 4G baseband processor with CPF flow
  • ARM Holdings - Design driven by DFM
  • Renesas - Multi level partitioning flow for giga-scale designs
  • STMicroelectronics - Hierarchical CPF usage in low power flow
  • Renesas/Cadence - Accurate clock tree prototyping

Functional Verification - 10 user presentations

  • Wolfson Microelectronics - Coverage driven requirements management
  • NoBug Consulting - Specman-driven real number modeling stimulus
  • Siemens - Specman-based solution for TLM2 verification component
  • STMicroelectronics - Using property checking to find bug in DMA block
  • Freescale - Formal verification of clock gating modules
  • Texas Instruments - Formal verification of a complex data preprocessor
  • IMMS - UVM based methodology for RFID smart sensor systems
  • STMicroelectronics - Metric driven verification flow for analog/mixed-signal
  • IBM - On the fly chip verification
  • Dialog Semiconductor - Auto-generated UVM framework

Logic Design - 3 user presentations

  • NXP - Security aware design with RTL Compiler
  • IMEC - Early power estimation for wireless baseband processors
  • NXP - Looking for un-initialized flip-flops

PCB Design and IC Packaging - 3 user presentations

  • ZMDI - Combining Spectre and PSpice
  • Mecadron - Creepage and air gap analysis
  • Freescale - Analog/mixed-signal die to package checks

System Design and Verification - 2 user presentations

  • ARM Holdings - Virtual platform applications and experiences
  • Texas Instruments - HW/SW co-verification of microcontroller

CDNLive! Taiwan 2012 Proceedings

Verification - 2 user presentations

  • ST-Ericsson - Low power verification without always-on domain
  • MediaTek - GPU platform verification and power estimation with Palladium

Digital Design - 3 user presentations

  • SIS - RTL Compiler experience
  • Altek - Low power methodology experience
  • IC Plus/Cadence - RC-DFT and Encounter Test experience

Digital Implementation - 3 user presentations

  • VIA - Clock concurrent optimization (CCOpt) and GigaOpt
  • GUC - Power, performance, area improvement with CCOpt
  • Socie - Design closure with 28nm low power design

Analog and Mixed-Signal - 3 user presentations

  • VIA Telecom - Front to back analog implementation in Virtuoso
  • Realtek - Virtuoso optimization for power reduction
  • Novatek - Simulating switched capacitor filters in MMSIM

IC Packaging and PCB Design - 3 user presentations

  • Inventec - GHz single-end signal design
  • CHPT - AC simulation for power impedance control
  • Pegatron - DC IR drop simulation using Allegro PDN solution

CDNLive! India 2012 Proceedings

(Note: Most of the India presentations had a Cadence co-author)

Verification - 8 user presentations

  • Texas Instruments - Accelerating verification with formal techniques
  • Hewlett-Packard - Coverage analysis using IEV and IMC
  • Texas Instruments - Challenges of generic IP verification
  • STMicroelectronics - SystemVerilog environment for imaging IPs/SoCs
  • Analog Devices - VMM to UVM migration
  • Freescale - Formal verification of designs with serial interface
  • Interra - Invalid instruction exit protocol verification
  • Rambus - Post-silicon test development for mixed signal IP

Digital Implementation - 8 user presentations

  • Freescale - On-die power distribution network for system-level analysis
  • Texas Instruments - Implementing multi-million GPU using hierarchy
  • Freescale - Reducing number of timing corners in sub-90nm nodes
  • Open-Silicon - Implementing 2 GHz+ ARM Cortex-A9 processors
  • Texas Instruments - Design closure flow for high performance designs
  • STMicroelectronics - Timing signoff convergence at deep submicron nodes
  • ARM - Power analysis for SoCs with CPF
  • Texas Instruments - QRC/ETS solutions for 28nm signoff

Digital Front End - 8 user presentations

  • Texas Instruments - Encounter Test on multimillion gate SoC
  • Freescale - Synthesis solution for rise/fall skew critical paths
  • Texas Instruments - Debugging test power issues with Encounter Test
  • Freescale - RTL Compiler low power asynchronous design implementation
  • Texas Instruments - Verify dynamic power sequencing checks using Conformal LP
  • Analog Devices - Universal logic equivalence checking methodology
  • Texas Instruments - SmartScan + OPMISR scan compression architecture
  • Freescale - Well biasing challenges and verification

Custom - 8 user presentations

  • Texas Instruments - Mining power intent for low power structural checks
  • Intersil - Behavioral modeling of split capacitor Sar ADC
  • STMicroelectronics - Layout automation using Modgen
  • Texas Instruments - Virtuoso Power System
  • PMC-Sierra - Timing models for analog IP considering crosstalk effects
  • Freescale - Analog mixed-signal verification for bi-directional interfaces
  • Texas Instruments - Assertion based self-checking analog designs
  • IBM - Verification of wire width, spacing, via-cut

System Verification - 8 user presentations

  • Lantiq - Emulation methodology for memory repair
  • STMicroelectronics - Coverage on Palladium XP
  • Texas Instruments - HW/SW analog/mixed-signal co-simulation of SoC
  • Freescale - RPP based platform for software development
  • ARM - Verifying Big.Little using Palladium XP
  • Samsung - PCIe based SSD verification using accelerated VIP
  • STMicroelectronics - TLM based software control of UVCs
  • Broadcom - Low power verification using common power intent

PCB Design and IC Packaging - 3 user presentations

  • Wipro - PCIe Gen2 & 3 simulations
  • Open-Silicon - DDR3 implementation in wirebond IC packages
  • Freescale - Die to die bonding using copper pillars

Alternate papers - 4 user presentations

  • Freescale - Macro placement algorithm for die size reduction
  • Sankalp Semiconductor - Virtuoso 6.1 features for improved cycle time
  • Xiliinx - Coverage unreachability analysis using IEV
  • Texas Instruments - RTL hookup bugs on Palladium XP

CDNLive! Israel 2012 Proceedings

Custom/analog - 1 user presentation

  • Spansion - Analog full-chip simulation flow using digital and analog back annotation

Digital Design - 3 user presentations

  • Altair Semiconductor - Using CCOpt to improve quality of results
  • Siano Mobile Silicon - Low power verification with Conformal LP
  • Texas Instruments - Synthesis constraints to last through physical design

Functional Verification - 4 user presentations

  • Karmel Electronic - Bottom up property-based formal verification
  • Freescale - Full chip CPF aware simulation challenges and techniques
  • Ceva - Customizing standard AXI VIP for proprietary bus
  • Texas Instruments - Using IFV connectivity for chip-level verification

System Development - 3 user presentations

  • Freescale - High-level synthesis for ASIC video processing design
  • Sigma Design - Vector driven Verilog testbench using Palladium XP
  • CSR - Palladium XP experience

Again, you can access these presentations here.

Richard Goering

 

 

 

 

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