A recent test chip tapeout using the Samsung 14nm FinFET process revealed significant progress in digital implementation at this new process node. Thanks to deep collaboration and extensive R&D investments in libraries, process, and tools, the digital implementation of the test chip was successfully completed in about eight weeks. The test chip tapeout was announced Dec. 20, 2012 by ARM and Cadence.
This chip is actually the second 14nm FinFET tapeout for Cadence and ARM. The first used an ARM Cortex-M0 processor and was based on an IBM silicon-on-insulator (SOI) process (you can read the press release here or a more detailed blog post here). The latest tapeout is the first 14nm tapeout to use a high-performance ARM Cortex-A series processor core -- the Cortex-A7 -- and it uses a Samsung bulk CMOS process. This digital implementation project was a three-way, geographically distributed collaborative effort across many time zones.
"There's this big scare factor about FinFETs and how they might affect your design methodology," said Mark Murphy, program director at Cadence. "The answer is that Cadence is ready, our partners are ready with us, and this [tapeout] paves the way for designers to quickly move forward." He noted that one designer concern is colorization for double patterning, but observed that Cadence "has already taken care of that" by providing double patterning awareness throughout its now-ready 20nm design flow.
A New Technology
FinFETs represent a disruptive new transistor technology that will profoundly impact the semiconductor industry. By providing much better performance and reduced power consumption compared to planar transistors, they provide a new pathway for Moore's Law beyond 20nm. In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor's elevated channel, or "fin." This provides much better control over current than planar transistors.
14nm FinFET architectures, however, pose the following challenges for custom/analog designers, requiring innovations in design tools and flows:
- The 3D structure of FinFETs results in new resistance and capacitance parasitics that must be extracted and modeled
- Additional design rules are needed for smaller geometries
- Interconnect delay effects occur across different layers
- Accurate new library timing models are needed
- 14nm complexity increases tool capacity needs
- Electromigration and power network analysis become more critical
Thanks to Cadence's substantial collaborative work with industry leaders, most of these challenges will be largely transparent to digital designers.
The tapeout project used a Cadence RTL-to-GDSII digital implementation flow including Encounter RTL Compiler, Encounter Test, Encounter Digital Implementation System, Cadence QRC Extraction, Encounter Timing System, and Encounter Power System. The Encounter Digital Implementation System provided double-pattern colorized placement, routing, and optimization. In addition to the ARM Cortex-A7 processor, the test chip includes foundation IP from ARM, designed using Cadence Virtuoso tools.
Cadence and ARM contributed more than just tools and IP. The test chip design was the result of a deep, "real time" collaboration involving engineers from Cadence, ARM and Samsung. Cadence engineers, for example, helped with place and route support, Cortex-A7 physical implementation, top-level test chip integration, and verification support. The IP, physical process rules and test chip were designed in parallel, with work done in Taiwan, Cambridge (U.K.), Austin, San Jose, Grenoble (France), and Seoul.
Of course, the Cadence-ARM-Samsung collaboration goes back much further than this eight-week digital implementation project. "A lot of work was done with Cadence and partners even before the project got underway," Murphy said. "It culminated in the ability to turn a project around very quickly once the technology comes on line."
The three-way collaboration and the availability of tools allowed the test chip implementation team to quickly and efficiently overcome any challenges. "The biggest challenge was that Samsung was doing process development during the same time that the IP was being developed, and while we were trying to integrate all this on a super short schedule," Murphy said. "The big challenge was integrating a brand new process and brand new IP at a new node with colorization challenges in a short time frame."
A substantial EDA R&D investment enabled the tools and the flow behind the test chip project. One thing that helped was collaboration between the ARM library design team and Cadence digital implementation engineers. For example, the library designers were able to take advantage of Cadence routing algorithms to create better routing access.
It will be some months yet before production ramps up, but from an EDA , IP and foundry perspective, the door is opening to enablement of advanced SoC designs using 14nm FinFET technology. A feature story at Cadence.com has further information.
Related Blog Posts
ARM TechCon: Inside Story of a 14nm FinFET Tapeout
ARM TechCon: Design at 14nm (or 10nm) - What's Going to Change
TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs
FinFETs, Tri-Gate Transistors Promise Low Power - But Pose Some Design Challenges