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Top Ten Cadence Community Blog Posts of 2012

Comments(0)Filed under: blogs, Industry Insights, Virtuoso, FinFets, advanced node, Verification IP, VIP, UVM, RF, SystemVerilog, TSMC, ARM Techcon, 20nm, Ubuntu, Top Ten, FinFET, videos, Cadence Community, 14nm, CoWoS, Sigrity, Tri-Gate, 16nm, cowbell, SpectreRF, 2012

In 2012, Cadence Community bloggers turned out over 400 posts in categories including Industry Insights, Functional Verification, PCB, IC Packaging, Custom IC, System Design and Verification, RF, Low Power, Mixed Signal, Logic Design, and Digital Implementation.

Below is a listing of the ten most read 2012 blog posts. One thing that leaps out at me is the keen reader interest in emerging technologies such as FinFETs and 3D-ICs. Readers also like practical posts that point the way to good information about products and methodologies. Our readers are both visionary and pragmatic!

1. SpectreRF AppNotes and Tutorials...Still One of Our Best Kept Secrets!

RF blog posts from 2011 and earlier are still attracting considerable readership, and this January 2012 RF post by Tawna Wilsey was the best-read 2012 Cadence Community blog last year.  It's a detailed and practical guide to information about the SpectreRF simulator.

2. UVM SystemVerilog Video Series Brings Verification World "More Cowbell!"

This Saturday Night Live reference in a Functional Verification post by Axel Scherer may have helped bring in readers, but there's also some good information about free UVM SystemVerilog videos.

3. Why Cadence Bought Sigrity - And How it May Change PCB Analysis

In July 2012 Cadence acquired Sigrity, a leading provider of signal integrity and power network analysis tools for PCB and IC package design. This Industry Insights blog post explains how Sigrity's technology fits with existing Cadence tools, and how the acquisition may bring "expert level" signoff tools into the design mainstream.

4. ARM TechCon: Inside Story of a 14nm FinFET Tapeout

At ARM TechCon in October 2012, Cadence announced a 14nm FinFET test chip tapeout using an ARM Cortex-M0 processor and IBM's FinFET technology. This Industry Insights blog post covers a technical session that explained the challenges that were encountered and the solutions that were developed.

5. Ubuntu Updates for 2012

In this System Design and Verification post, Jason Andrews provides an update on how to run the Virtual System Platform and Cadence Incisive simulator on the latest version of Ubuntu.

6. FinFETs, Tri-Gate Transistors Promise Low Power - But Pose Some Design Challenges

This Industry Insights post gives a quick overview of FinFET technology, notes advantages, and talks about the challenges that custom/analog designers will face. It also describes needed tool capabilities.

7. Best Practices for Selecting and Using Verification IP (VIP)

Should you buy VIP or build your own? What should you consider in selecting VIP? And how can you make best use of it once you have it? This Industry Insights blog post answers those questions.

8. Things You Didn't Know About Virtuoso: Change is Here to Stay

In this Custom IC blog post, Stacy Whiteman shows how to change the values of device instance parameters in Virtuoso without having to edit the schematic.

9. TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

At the TSMC Open Innovation Platform Ecosystem Forum in October 2012, TSMC executives provided updates about the company's 20nm process, 3D-IC technology, and 16nm FinFET process. This Industry Insights post has the details.

10. TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

As announced at the 2012 Design Automation Conference, and reported in this Industry Insights blog post, Cadence helped refine the methodology and provided tool support for the TSMC chip-on-wafer-on-substrate (CoWoS) process.

Thanks for reading Cadence Community blogs in 2012! We have much more in store for 2013, and we always welcome your feedback.

Richard Goering

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