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Martin Lund Keynote: Time to Rethink Semiconductor IP “Reuse”

Comments(0)Filed under: Industry Insights, IP, IP Reuse, Moore's Law, protocols, PCI Express, packaging, semiconductor IP, latency, silicon IP, IP ecosystem, Martin Lund, Lund, IP Factory, Design and Reuse, SoC: IP-SOC, Grenoble, Design & Reuse

People have been talking about semiconductor IP "reuse" for many years, but is IP really reusable as is? It's increasingly unlikely, according to Martin Lund (right), senior vice president of the SoC Realization Group at Cadence. In a recent keynote speech, Lund said that continuous changes in standards, technology, and requirements mean that IP cores must be configured in an "IP Factory" to meet the needs of a given system-on-chip (SoC).

Lund gave the keynote speech at the IP-SOC 2012 conference in Grenoble, France Dec. 4, 2012 (I "attended" the keynote via a recorded presentation). The speech was titled "Cloud and Mobility - Disrupting the IP Ecosystem."

"In the semiconductor space there are both huge challenges and huge opportunities," Lund said. "The stakes have never been higher. The pace of technology adoption is immense." This pace includes servers, tablets, automotive electronics, social media, and especially the upcoming "Internet of things" that could result in 50 billion connected devices by 2020.

Before discussing IP reuse, Lund cited "seven disruptions that are coming our way," including:

  • Moore's Law is slowing down. This is a "fact" in spite of a lot of pressure to find ways around it - such as extreme ultraviolet (EUV) lithography, fully depleted silicon, 3D-ICs, and more.
  • Increasing package complexities. 2.5D interposer, 3D-IC, and POP (package on package) configurations mean new design rules and approaches to testability.
  • Rising development costs. Mask costs are going up, design rules are getting more complex, and there may be hundreds of timing corners to close at advanced process nodes.
  • Increasing number of IP cores. SoCs may have hundreds of cores. But if the quality of the cores does not increase, the probability of a fast yield ramp-up will go down.
  • Escalating protocol complexities. One way to look at this is how many pages a spec requires. The PCI Express Gen3 spec has 860 pages. There's enormous pressure on design teams to understand and implement this complexity, and this is a place where IP can create some real value.
  • Growing importance of latency. A lot of design effort and complexity is going into "hiding the latency" with techniques such as cache coherent interconnect.
  • Accelerating time to market pressures. We used to have a couple of years between new products -- now they're out every year. The pressure of meeting deadlines is enormous.

One Size Does Not Fit All

One consequence of these disruptions, Lund said, is that "a one-size-fits-all IP approach doesn't work anymore. Every SoC has different requirements." He said that the traditional notion of IP reuse "is suffering from rapid changes in standards, in technology, and in requirements."

To provide an example, Lund pointed to PCI Express, which has gone through three standards in ten years (with Gen4 coming out soon). A number of ECNs have provided modifications to the standard. "This is a continuous train of change," Lund said. "There's no ‘build it once and we don't have to touch it anymore.'" On the other hand, he noted, derivatives "are a form of reuse that makes sense."

Lund also pointed to changes in Ethernet standards and DRAM interfaces, and even showed how a single product family - the Kindle - has changed its processor, storage, display, and interfaces over successive generations. His conclusion is that "the old ways of IP don't work anymore." These "old ways" include the IP Bazaar, where price and availability are the driving concerns, and the IP Mall, where products are provided off the shelf.

So what does work? "I suggest you have to take a factory approach," Lund said. "You say yes there will be changes, and you build the machine that delivers the IP. That's the product. The IP is a by-product of that innovation." The IP Factory, he said, is "quality focused, integration optimized, and requirements driven. We'll take your requirements and generate your core."

Cadence is using the IP Factory approach to deliver customized, on-demand IP solutions, Lund said.  This includes over 3,100 unique memory configurations, over 6,000 memory models, and over 40 verification IP protocol solutions. "Taking an IP Factory approach, we think we can help bring the IP ecosystem forward, and help to calm some of those challenges the semiconductor industry is faced with," he concluded.

Richard Goering

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