Most system-on-chip designers have two things in common - use of ARM physical and/or processor IP, and a mandate to reduce power consumption. There's a wealth of information on low-power design with ARM IP in a newly available video, as well as presentation slides, from an hour-long presentation at the Low-Power Technology Summit at Cadence Oct. 18, 2012.
The presentation was given by Sathya Subramanian (right), technical marketing manager at ARM, and was titled "Low-Power Design with ARM® Physical IP and POPTM IP." Subramanian discussed ARM Artisan standard cells, the ARM Power Management Kit (PMK), power management in ARM Artisan memories, ARM POP (Processor Optimization Pack) IP, and ARM and Cadence R&D collaboration in the development of POP IP.
The ARM presentation is one of several that you can access here (Cadence Community log-in required to view proceedings - good time to sign up if you don't have one). For an overview of the Low-Power Technology Summit, see Pete Hardee's recent blog post. I previously blogged about the keynote speech by Jan Rabaey, professor at U.C. Berkeley, and a low-power panel that concluded the summit. What follows is a brief review of Subramanian's presentation.
Starting with Physical IP
Subramanian began by presenting an ARM perspective on low power. As new, mobile technology continues to proliferate, there's strong pressure to get the highest possible performance per watt. Scaling helps with performance, but often worsens leakage. How can we mitigate the challenges of scaling? "ARM's view is that low power optimization must start at the physical IP level," he said.
Indeed, ARM physical IP uses the most commonly employed low-power techniques today, including clock gating, power gating, multi-Vt, multi-Vdd, adaptive scaling, retention/isolation, and power network/power switches. "What will be interesting at 20nm and below," he said, "is how we'll deploy these techniques and still get the juice out of the latest technologies."
ARM Artisan standard cells use low-power architectures with such features as low-power flops, multi-bit flops, and high-density flops. In collaboration with foundries and EDA vendors including Cadence, ARM engineers examine flops, clocks, logic, wire, memory, and static components to perform cell-level optimization.
Power Management Kits
Power optimization must also occur at the block and chip levels, where decisions must be made about power shutoff, power domains, and voltage islands. This is where the ARM Power Management Kit (PMK) comes into play. It includes the following components:
- Power gates
- Level shifter and isolation cells
- Retention flip-flops
- Back biasing support
- "Always on" buffers
Subramanian offered an overview of some of the strategies enabled by the kit, including power gating switches, power gate insertion, and retention flops. He showed how the PMK fits into the standard EDA flow and works with the Common Power Format (CPF). The EDA flow with PMK has a few additional considerations, such as the need to verify power and ground connections.
Subramanian also conveyed some ARM recommendations for power supply routing. The company recommends that designers use a "lower 2D supply grid" and use lower metal layers to do the power distribution at the cell level. This has a number of benefits but may also come with some overhead in terms of layer usage.
Power Management in ARM Artisan IP Memories
ARM has clearly done a lot of power management work in its memories, and Subramanian went into a "deep dive" about some of the low power techniques the company uses. He first noted that there are two basic modes - one with power gating built into the memories, and one without built-in power gating. The latter mode employs a user controlled external power supply.
Subramanian described active and standby modes, power gating compile time option, retention mode with and without integrated power gating, and power down mode with and without integrated power gating. A chart showed the tradeoffs for these techniques in terms of leakage savings vs. wake-up time.
ARM POP IP and Cadence Collaboration
Processor IP comes with a number of technical challenges, and ARM POP IP can help. This optimized IP has three main attributes:
- Core-optimized physical IP is tuned to a specific process
- ARM certified benchmarking makes sure the core will go through an implementation flow
- ARM "implementation knowledge" offers continuous improvement of power, performance and area results
ARM and Cadence R&D have collaborated extensively on POP IP. In one project, the companies worked together to improve POP IP to leverage Cadence CCOpt (clock concurrent optimization) technology for an ARM Cortex-A9 on a TSMC 40LP process. In another, the companies worked to achieve the highest possible Cortex- A15 performance target using the Cadence Encounter Digital Implementation System. A third project found the best performance/power tradeoff for the Cortex-A15 targeting the tablet market segment.
Finally, Subramanian discussed the first ARM Cortex-A15 tapeout on a TSMC 20nm process, made possible by close collaboration between Cadence, ARM and TSMC. This industry milestone was announced in Oct. 2011.
Again, you can access the ARM presentation and video, along with other proceedings from the Low-Power Technology Summit, at the archive page that was set up earlier this month.