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Archived Webinar: New Technology Attacks the Verification Debug Bottleneck

Comments(0)Filed under: Industry Insights, verification, Functional Verification, Incisive, Simulation, Debug, webinar, debugging, cause analysis, Incisive Debug Analyzer, verification debug, playback debugger, smart log

Verification debug hasn't exactly been a hotbed of technology innovation, even though verification teams report that debugging can consume more than 50% of the overall verification effort. A recently archived Cadence webinar reviews common debug challenges and shows how the new Incisive Debug Analyzer, announced in October, offers new technology that can help engineers break through the debug bottleneck.

This well-attended webinar was titled "Accelerate Your Verification Debug with the New Incisive Debug Analyzer." Kishore Karnane, product marketing director, introduced the webinar by noting that debug has become the main bottleneck in verification. "We've heard from customers that over 50% of the effort today is in debug," he said. Moreover, he noted, it's becoming almost impossible to debug at the signal level, because verification teams are shifting their methodology from the signal level to transaction-level and class-based verification.

Karnane said that Cadence customers have identified the following debug challenges:

  • Data explosion. Designs are complex, and log files and coverage databases are large.
  • The need to re-run simulations multiple times, starting all over again if a problem occurs.
  • Inefficient methods of filtering log files and searching for signals.
  • An unguided debug environment with no clues on where to search for failures.
  • Demands for collaboration across global teams, and the need to share data.
  • The tradeoff between computing resources and human resources (you can speed up computers, but you still need humans to debug potential problems).

What's needed is new technology that reduces the amount of time that humans have to spend in front of computers debugging - and that's where the Incisive Debug Analyzer comes in. Karnane called it a "new concept in debug" that provides interactivity in a post-processing debug environment. Thus, engineers have access to all the data files and only need to run the simulation once.

The Debug Analyzer consists of four core elements (right) that are tightly integrated and synchronized in a single multi-pane debugging window. It leverages the existing SimVision environment for waveform and transaction-level debug. Karnane described the four core elements as follows:

  • The Playback Debugger makes it possible to step or jump through time to any source code line or variable - even backwards. As a result, teams only have to run simulation once to get the data they need for debug.
  • Cause Analysis helps users answer questions like, "why have I reached this code" or "how did I arrive at this value." It will take users to a source code line where an error was made or a value was selected. The analysis shows causality relationships and provides some leads users can follow to debug the code.
  • Exploration, or "Smart Search," provides a quick way to explore the verification environment. It can find interesting simulation items such as a given value. Or, a user could find all the places where the word "parity" is used, from the testbench to the RTL.
  • Smart Log integrates messages from any platform, including HDL, testbench, C/C++, SystemC, and assertions. It provides the text, the line, the time, and the verbosity, and users can change the verbosity. Smart filtering actions include keep, remove, and add.

Much of the one-hour webinar is a hands-on demo given by Nadav Chazan, principal solutions engineer at Cadence. The demo uses the Incisive Debug Analyzer to track down a parity mismatch error. The example uses mixed VHDL and Verilog RTL, and a testbench written in the Specman e language. After the demo, a poll showed that 60% of the webinar attendees regarded the Playback Debugger as the most valuable of the four key features listed above.

In summary, Karnane noted, the Incisive Debug Analyzer improves productivity and predictability, with some customers reporting a 40% savings in debugging time and effort. Scheduled availability is end of 2012 for the e language and June 2013 for SystemVerilog.

Cadence Community members can access the webinar here (quick and free registration if you're not a member).

Richard Goering



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