All 20nm test chips are learning experiences, and a recent tapeout of a 20nm Cortex-M0 test chip by ARM engineers was no exception. Completed in June 2012, the test chip design used a Cadence digital implementation flow. The story of the test chip is told in a new guest partner blog (I'm the "guest" writer) at the ARM web site.
The test chip was the first project for the new ARM design center located in Hsinchu, Taiwan. One goal of the project was to provide feedback to ARM's physical IP group about the quality and usability of its standard cells and RAM. The test chip project also provided a "test drive" of the 20nm capabilities in Cadence tools, including RTL Compiler, Encounter Digital Implementation System, Encounter Timing System, Encounter Power System, and QRC Extraction.
As reported in the ARM guest blog, here are some of the lessons learned:
- The Cadence tools are ready for 20nm, with fewer than expected problems relating to routing or double patterning.
- Designers had to cope with ongoing changes in the design rules and the resulting impacts on placement and routing.
- Most of the design challenges were around routability and the need to understand local density.
- To avoid using up routing resources, routing pitches need special attention on double patterning layers.
- The power delivery network must be designed carefully so local routing resources are not blocked.
ARM and Cadence went through this learning exercise so you don't have to. When full 20nm production is underway, you'll want a mature ecosystem where everything is in place to design and manufacture a chip as quickly, efficiently, and inexpensively as possible. That ecosystem must include verified physical IP, design IP, a comprehensive EDA tool flow, and foundry support. At this point it appears that all these pieces are falling into place.
For more detail, see the ARM guest blog here.