Home > Community > Blogs > Industry Insights > is fast spice simulation hitting a wall
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Is Fast SPICE Simulation Hitting a Wall?

Comments(2)Filed under: Industry Insights, Virtuoso, Analog, verification, Mixed-Signal, mixed signal, SPICE, timing, parasitics, power gating, Fast SPICE, power domains, hierarchy, transistor level, memory characterization, fast MOS, circuit simulation, partitioning, UltraSim, full chip, event-driven simulation

The transistor-level SPICE simulator has been the gold standard for custom/analog verification for decades. But SPICE is too slow for many applications in which transistor-level accuracy is needed. So-called "Fast SPICE" simulators can provide considerable speedups -- but current Fast SPICE technology is running out of steam today. Looking towards the future, a new generation of technology is needed.

"Fast SPICE is one of the fastest evolving EDA technologies out there," said John Pierce, product marketing manager for circuit simulation at Cadence. "It needs to reinvent itself on a regular basis. Verification requirements change, design architectures change, and the same fundamental need is there for accurate transistor-level results."

First, let's consider what Fast SPICE is - and is not. It does provide a transistor-level simulation, but unlike SPICE, does not do a full matrix solution for the entire circuit under test. It may provide capacity and performance increases of 20-30X over SPICE, while providing accuracy to within 1% to 10% of SPICE, depending on the tool that you're using and the problem you're trying to solve.

Fast SPICE does not replace the SPICE simulation used by analog circuit designers. Fast SPICE is, however, widely used for memory characterization and design, critical path timing, and full-chip mixed-signal SoC simulation.

Collection of Techniques

Rather than a single technique, Fast SPICE is a collection of approaches. It started with faster, simplified MOSFET models that use model reduction techniques, and as such the early Fast SPICE simulators were sometimes called "Fast MOS" simulators. Other Fast SPICE techniques may include the following:

  • Event-driven simulation as opposed to convergence at each time point
  • Leveraging multi-rate simulation to avoid solving everything at every time step
  • Partitioning the design into smaller sub-circuits that can be solved individually
  • Hierarchical simulation (for example, simulating one memory cell and repeating the result many times)

One Fast SPICE simulator that uses advanced partitioning algorithms and true hierarchy is the Virtuoso UltraSim Full Chip Simulator. It accelerates pre and post-layout verification for memories, custom digital, and mixed-signal SoC designs. UltraSim is adequate for many of today's designs, but for the future -- particularly for the design of large memories -- a new level of technology will be needed.

Fast SPICE simulators such as UltraSim use partitioning and hierarchy

So What's the Problem?

Fast SPICE is running into problems with partitioning and hierarchy. "We went from an era when partitioning techniques were still working, to an era where we have a lot of low power techniques like power gating," Pierce said. "That completely breaks old partitioning methods. You used to have a lot of small partitions that were fast to simulate, and now you're getting larger and larger partitions, slowing the simulation."

Pierce explained that traditional partitioning technology is based on channel-connected partitions. But now a design may have several supply domains, each of which has various modes such as sleep and shutoff. As a result, partitioning techniques break down, because there is no longer a direct connection to Vdd or a power line. The channel connection is no longer visible to the Fast SPICE simulator.

Moreover, increasing parasitics in designs make it difficult or impossible to use hierarchy, especially for memory design and characterization. Pre-layout simulations are not as valuable, and more requirements are placed on post-layout simulation. "As soon as I put all those parasitics into my memory design, the hierarchy is no longer present," Pierce said. "I no longer have a matching hierarchy."

A New Generation of Fast SPICE Technology

What's needed, said Pierce, is breakthrough technology that delivers the speed gains Fast SPICE provided in the past. "We need to reinvent Fast SPICE techniques to overcome the challenges presented by increasing parasitics and low power circuit structures," he said. "We need a different way to improve performance and not base it on a method that depends on not having parasitics in your design."

What this calls for is a "step function" improvement in performance, along with technology that can handle the capacity of large designs including parasitics.

Another requirement is for Fast SPICE simulators to plug directly into existing design and verification environments, rather than running as isolated point tools. For memory designers, a close connection with a memory characterization tool is crucial. And timing, noise and power information from characterization needs to be provided in a format that can plug into a digital implementation and verification flow.

"Fast SPICE technology really needs to re-invent itself," Pierce concluded. Indeed, it may become a focal point for the next wave of innovation in EDA.

Richard Goering



By spiceUser1123 on November 19, 2012
What about using ROMs for parasitic RC nets? (Reduced Order Models)
They work seem to work fine for graph-based and path-based STA.

By Kevin Cameron on November 19, 2012
The thing that needs to be done is a mathematical reduction of the models so that rather than simulating tranistors you simulate functional blocks with similar accuracy but without having to resolve the internal contention between devices. Unfortunately things like the BSIM models are written in a way where the mathematical reduction is not possible by analytic means, but there are other approaches that should work (ask me later). A more pressing problem is that while such models could be created in Verilog-AMS, there is no standard way to back-annotate them (the SPEF part above), so most folks are working from full extraction instead, and working back from that to get the functional blocks is painful.

Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.