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Video: Cadence VP Tom Beckley Discusses Advanced Node Custom/Analog Challenges

Comments(0)Filed under: Industry Insights, Virtuoso, Analog, advanced node, DRC, Double Patterning, 28nm, analog/mixed-signal, 20nm, Cadence, design rules, LVS, custom/analog, in-design signoff, Beckley, triple patterning, local interconnect, Goering, partial layout

Any discussion about advanced node (below 28nm) that focuses only on digital design is missing an important part of the story. Custom/analog design must be considered too, and that's the subject of a video interview with Tom Beckley, senior vice president of R&D for Custom IC and Simulation at Cadence.

In this 3 ½ minute interview, I asked several questions, including:

  • There's been a lot of discussion about advanced node digital design. Does custom/analog need to be part of the advanced node discussion, and if so why?
  • What are custom/analog designers most concerned about?
  • What are the concerns of custom digital designers working on memories and standard cells?
  • Double patterning is mostly transparent to digital designers. What about custom/analog designers? How does their design flow change?
  • Do we need a new custom/analog design methodology below 28nm, and if so what would it look like?

For answers, click on the video icon below or click here.

Tom Beckley has more to say about advanced node design in a new viewpoint at Electronic Design, titled "Will Layout-Dependent Effects (LDE) Stand Between You and Your Next Smart Device?" To read it, click here.

Richard Goering

Related Blog Post

ISQED Keynote: 20nm From a Custom/Analog Perspective

 

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