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ARM TechCon: Inside Story of a 14nm FinFET Tapeout

Comments(0)Filed under: Industry Insights, ARM, lithography, Virtuoso, Encounter, FinFets, IBM, SOI, PDK, SPICE, Double Patterning, ARM Techcon, Cadence, extraction, QRC, routing, design rules, signoff, Altos, Liberate, Variety, standard cells, test chip, placement, Cortex-M0, FinFET, electromigration, 14nm, LELE, Liebmann, EM, Gerousis, routability, library characterization, BSIM, 14SOI

The next frontier in semiconductor design is the 14nm process node, and it will come with a new type of transistor, the FinFET. 14nm FinFET technology moved closer to reality at the ARM TechCon conference Oct. 30, 2012, where a Cadence sponsored technical session announced a 14nm test chip tapeout using an ARM Cortex-M0 processor and IBM's FinFET process technology.

FinFETs promise greatly reduced power for a given level of performance.  In a FinFET, the field effect transistor (FET) gate wraps around three sides of the transistor's elevated channel, or "fin." This approach provides much more control over current compared to planar transistors. A previous blog post gives a brief overview of FinFET technology and design challenges.

Here are some quick facts. Cadence, IBM and ARM taped out three versions of the test chip in order to evaluate different routing strategies (uni-directional, bi-directional with single cut via, and bi-directional with via bar). In addition to the ultra low power Cortex-M0 processor, the chip included SRAM memory blocks along with other blocks that provided characterization data for ARM Artisan foundation IP for 14nm FinFET design. Validation of this physical IP was one of the goals of the project.

The test chip uses IBM's 14nm silicon-on-insulator (SOI) technology. The chip was implemented using the Cadence Encounter Digital Implementation System, and was based on ARM 8-track 14nm FinFET standard cell libraries designed with Cadence Virtuoso tools.

Tackling 14nm Challenges

The challenges behind the test chip development came to light in a presentation prepared by Lars Liebmann, IBM fellow and renowned lithography expert, and Vassilios Gerousis, distinguished engineer at Cadence. Unfortunately, Liebmann was stranded on the east coast by Hurricane Sandy and unable to attend ARM TechCon.

Gerousis opened the presentation by noting that "advanced technology takes a lot of work. Good collaboration is required to implement 14nm." This collaboration between Cadence, ARM and IBM included cell library design, fab technology, and tool readiness. It was a multi-year partnership almost three years in the making, Gerousis noted.

Presenting Liebmann's slides, Gerousis noted that 14nm and 20nm share some challenges in common -- most notably, a 64nm metal pitch, which gives rise to a requirement for double patterning. But FinFETs present some new challenges. For example, the 3D architecture of FinFETs introduces more parasitic effects, and has a big impact on coupling.

FinFETs will require some extra work and new understandings from standard cell designers. From a process point of view, it's best to pattern a "sea of fins" at a sub-lithographic pitch, select a subset that will become active fins, and remove the rest. Cell height is defined by both the number of metal tracks and number of fins. Transistor width is defined by the integer number of fins. A tight fin pitch allows the best efficiency for device tuning. 

"Because the FinFET pitch is very small, you need to do more advanced lithography," Gerousis said. "And that really means it needs to be directional, it needs to be gridded, and that could impact the tool set."

Liebmann's slides also went into some detail about double-patterning and layout decomposition, showing how the litho-etch, litho-etch (LELE) double-patterning approach works at 14nm. In presenting the slides, Gerousis noted the importance of color-aware placement and routing, and observed that Cadence offers the ability to do colorization "on the fly" in a correct-by-construction manner.

Cadence 14nm FinFET Methodology

Moving to the Cadence part of the presentation, Gerousis described the design methodology behind the 14nm test chip. First, standard cells and IP were implemented using the Virtuoso custom design platform with a 14nm process design kit (PDK). The Liberate and Variety tools that Cadence acquired from Altos Design Automation allowed variation-aware timing and power characterization. Secondly, the Encounter platform provided a full RTL-to-GDSII flow, supported by the latest 14nm technology files. Finally, signoff was provided using the Cadence QRC extractor, Encounter Timing System, and Encounter Power System.

The FinFET custom design methodology includes Virtuoso schematics and layout, QRC extraction, Physical Verification System (PVS), simulation with Spectre, and BSIM FinFET models. Layouts and schematics can be easily migrated from planar transistors to FinFETs. SPICE FinFET models are somewhat different from planar transistor models, however, as they must include the number of fins.

"The toughest part of the entire [flow] with a FinFET is really the extraction," Gerousis commented. This is because extraction must cope with resistive networks and extensive coupling between devices. Further, he noted, "you really need transistor-level extraction because your voltage and current is not uniform across the gate."


Cadence custom flow for 14nm FinFET

The Encounter 14nm flow offers FinFET-ready, double-patterning correct physical implementation and signoff. It reads in 14nm design rules and does color-aware placement and routing. The digital flow includes timing, power, IR drop, and electro-migration (EM) analysis and signoff. Gerousis noted that EM will be "a big issue at 14nm and could be very restrictive in terms of what you can do in your design."


Cadence digital flow for 14nm FinFET

Developing Test Chips

Gerousis noted that IBM, ARM and Cadence worked together as a team to develop the test chips. This collaboration included an early 14SOI routing experiment in August 2011, which provided IBM with some early feedback on how their technology definition impacted routability. The partners continued with double-patterning aware router and flow development, and worked together to evaluate tradeoffs between yield and routability.

IBM and Cadence developed a set of routing experiments to quantify tradeoff questions. The experiments produced routability metrics for design densities ranging from 65% to 85% utilization. One finding was that 14SOI double-patterning clean routing has no impact on wire length, but has some impact (generally less than 10% increase) on via count. Finally, these routing experiments were extended to hardware with the tapeout of three versions of a test chip.

"This was done with great collaboration between three companies - IBM, ARM and Cadence," Gerousis concluded. "I cannot emphasize how important this early collaboration is." The chips were taped out several months ago, and the partners are now waiting for silicon to come back.

Richard Goering

Related Blog Posts

CDN Live! -- IBM Expert Quantifies Design Impact of Double Patterning

TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs


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