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Q&A: TSMC R&D VP Cliff Hou Discusses 20nm, CoWoS Multi-Die Packaging, and FinFETs

Comments(0)Filed under: Industry Insights, Double Patterning, stacked die, 3D, TSV, TSMC, 20nm, 3D-IC, design rules, 2.5D, FinFET, OIP, DPT, CoWoS, Hou, TSMC Forum, Open Innovation Platform, 16nm, gate density, Cliff Hou, reference flow, TTS

The recent TSMC Open Innovation Platform (OIP) 2012 Ecosystem Forum marked the release of 20nm and chip-on-wafer-on-substrate (CoWoS) reference flows, as well as new insights about the giant foundry's plan for 16nm FinFETs. I blogged about the keynote speeches here. Separately, I interviewed one of the keynote speakers -- Dr. Cliff Hou, vice president of R&D -- later in the day. Excerpts from our conversation follow.

Q: Dr. Hou, what does your work involve at TSMC?

A: My team is responsible for design enablement for our customers. To do design enablement, we need to work with ecosystem partners. Right now we cover both EDA and IP. We find all the issues first. Then we work with partners to solve the issues, and provide our solution to our customers.

Q: TSMC recently announced a 20nm reference flow that is "double patterning aware." Why is this a significant development?

A: At 20nm the challenge is double patterning, and it will impact a lot of tools. If the customer tests them one by one it will probably take one to two years before they can start the design. We don't want to see that; we want the customer to use this technology as early as they can. To do that we have to work with partners, run through all the issues, and clean up those issues before the customer sees them.

Q: When do you expect volume production for 20nm?

A: Customers can start designing now. The process is ready for mass production. Our risk [early] production is in Q1 2013. Normally customers take 9 months to one year for implementation, so I would roughly guess [volume production] would be early 2014.

Q: How does the new 20nm reference flow address the needs of digital and custom/analog designers?

A: Digital designers want to squeeze out more density. Analog designers are more concerned about mismatch. With double patterning, they want to pre-assign some coloring. So we worked with partners so that analog designers can pre-assign color for critical circuits. And we also provide a utility to let them check whether their assignment is manufacturable.

Custom design is relatively straightforward. We provide design rule checking, and also some utilities to help designers debug and fix violations. We embed rules in the router. We spent a lot of time working with partners so routing is double-patterning aware.

Q: What does double patterning require from digital ASIC designers? You said in your keynote that the reference flow makes double patterning "almost transparent."

A: Most of it is transparent because rules are embedded into the router. For most of the design, they just do the routing as they did for 28nm.

Q: What kinds of double patterning rules are needed, and how restrictive are they?

A: Double patterning rules are mostly about spacing. They have some restrictions, but once you get familiar with them you can still achieve a pretty decent gate density. For example, from 28nm to 20nm, the standard cell gate density shrink ratio can still achieve 1.9X. That's pretty close to the shrink from previous generations.

Q: You've also announced a CoWoS reference flow. Currently CoWoS allows designers to place dies side-by-side on a silicon interposer substrate, allowing "2.5D" integration, not 3D stacking. Will TSMC also support 3D stacked die?

A: Yes, but we will give it another name. Internally we call it TTS, through-transistor substrate. TTS is true 3D stacking; some people call it TSV (through-silicon via). We're working on it.

Eventually CoWoS will give you the backbone for creation of the whole system. Chips will connect through the CoWoS. But this chip can be one chip, or multiple chips, and with [stacks] of multiple chips you can use TTS or TSV to connect them. That is why we decided to do CoWoS first. It will all be integrated through CoWoS. That's our vision.

Q: What kinds of chips can be integrated into a CoWoS package today?

A: Memory, logic - it can be anything. The only thing is, if the chip is from a different foundry or supplier, we need to go through a validation process first. TSMC and the supplier have to partner together to make sure it will be manufacturable when designers put it in the CoWoS.

Q: What's the ecosystem for CoWoS? Who does packaging, assembly, test?

A: Currently CoWoS is all done by TSMC, but we are open. The reason we do CoWoS by ourselves, in the beginning, is that it requires some technology to drive other solutions through.  When the partner ecosystem is ready, we will be open to working with our partners.

Q: How does the CoWoS reference flow differ from a single-chip reference flow?

A: The top chip design will be the same. But you have to do bump assignment and RDL routing, and you have to comply with the CoWoS interposer substrate design requirement. Then you have to do the substrate design, and integrate it together. Then you have to do electrical and physical verification, and thermal and DFM. This is all included in our reference flow.

One challenge is that the databases of the chip design and substrate design are different, so you have to understand both. At this moment we use the Cadence platforms [Encounter and Allegro] to integrate the information from both parts.

Q: If you're designing a chip you might want to integrate into CoWoS at some point, are there additional design considerations?

A: Yes, one is the bump assignment. Another challenge is known good die testing. It's difficult to do testing when you have multiple die you want to integrate. Customers need to do the individual die testing, and when they connect individual die and integrate them into the CoWoS they have to do integrated test. We have to make sure the yield of the interposer is higher than 99.8%.

Q: Let's move on to FinFETs. You're talking today about 16nm FinFETs. Why 16nm?

A: We made some calculations based on performance and dimension. We compared to 20nm based on power and performance. We think what we offer will be in the middle of 14nm and 20nm, so we call it 16nm. The 16nm FinFET is very close to 14nm. At 16nm there are only FinFETs, no planar [transistors].

Q: What do you see as the advantages and design challenges of FinFETs?

A: Advantages are speed and power reduction, especially in low Vdd. Challenges include new design rules. All of the fins are digital fins, so this causes new design rules. Also, ESD [electro-static discharge] and thermal are issues that need to be considered.

Q: Will the digital SoC designer see anything new with FinFETs?

A: I think it will be pretty transparent. The metal layer is the same as 20nmSOC -- only the device is different. SoC designers who work with IP at the chip level won't see any difference, but the IP designer has to learn to use digital fins. The challenge will be on the IP developer.

Q: When do you expect to have a PDK and reference flow for FinFETs?

A: The early PDK and reference flow will be ready by January of next year. The complete flow will be in the October 2013 time frame. Then you can do a real product and tape out.

Richard Goering

Related Blog Post

TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

Photo of Dr. Hou by TSMC Ltd.


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