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Cadence at ARM TechCon – Verification IP, 14nm FinFET, Low Power, Mixed Signal, and More

Comments(0)Filed under: Industry Insights, ARM, low power, virtual platforms, Mixed-Signal, Faraday, Verification IP, VIP, embedded software, ARM Techcon, Cortex, Cadence, ACE, virtual prototypes, Cortex-M0, CEVA, cache coherent, Hisilicon, embedded systems, AMBA VIP

With nine technical paper presentations, six sponsored sessions, demos, and exhibits, Cadence will have a strong presence at ARM TechCon in Santa Clara, California Oct. 30-Nov. 1, 2012. Cadence papers and sessions will cover topics including advanced-node digital, mixed-signal, low power, verification IP (VIP), 14nm FinFETs, and embedded software development with virtual prototyping.

Cadence is also revving up for ARM TechCon with a pre-conference announcement of three successful verification projects using Cadence AMBA VIP.  Representatives of CEVA, Faraday Technology Corp., and Hisilicon Technologies Co. Ltd affirmed how the AMBA VIP, which supports AMBA 4 protocols including ACE cache coherency, saved weeks or months of verification time. A press release provides more information about these engagements, and a new feature page on Cadence.com describes AMBA VIP and provides resources such as videos, articles, and blogs.

ARM TechCon is actually two conferences in one - a Chip Design Conference Tuesday Oct. 30, and a System and Software Design Conference Oct. 31 and Nov. 1. Here's what you can expect from Cadence during each of these conferences.

Chip Design Conference - Oct. 30, 2012

Exhibit: At Cadence booth #36, you can learn about an RTL-to-GDSII flow for ARM Cortex-A processors. Cadence will also demonstrate a mixed-signal solution for ARM Cortex-M0 based designs (for more information on this solution, see this recent ARM blog post).

Sponsored Sessions - Room #204

10:30 - 11:20 Automating the verification of SoC interconnect fabrics
Huzaifa Dalal, Senior Product Marketing Manager - VIP, Cadence and Mirit Fromovich, Staff Solutions Engineer, Cadence

11:30 - 12:20 Power efficient big.LITTLETM processing: lessons learned from a 28nm multi-core Cortex-A7 low-power implementation 
Paddy Mamtora, Group Director, Cadence

1:30 - 2:00 Designing with 14nm FinFET Technology
Lars Liebman, STSM, Distinguished Engineer, Design-Technology Co-Optimization, IBM
Vassilios Gerousis, Distinguished Engineer, Cadence

2:10 - 3:00 Implementing Advanced Next Generation Mali T6XX GPUs with Cadence Encounter Digital Flows
Sanjiv Taneja, Vice President, Research and Development, Cadence

3:10 - 4:00 Designing mixed-signal with ARM CortexTM-M0 
Luke Lang, Director of Engineering, Cadence

4:10 - 5:00 Optimizing Power Efficiency in GHz+ Quad-core ARM Cortex-A15 Processor Hardening 

Technical Papers (click on links for details):

ATC-101 Tues @ 10:30am
Silicon Validation of GLOBALFOUNDRIES-Cadence Digital Design Flow in 28nm using ARM Physical IP

ATC-103 Tues @ 10:30am
Advantages of NVMe for Low-Power Storage
Bob Pierce

ATC-106 Tues @ 11:30am
Building Your UVM Environment for ACE-Based Verification
Mirit Fromovich, Tamar Meshulum

ATC-112 Tues @ 2:10pm
A Novel Power Intent Specification Methodology for the IP Developer
John Decker

ATC-110 Tues @ 2:10pm
Cache-Coherent Interconnect Complexity, Verification, and Performance Analysis
Nick Heaton, Stewart Penman, Paul Martin (ARM)

ATC-117 Tues @ 3:10pm
Improving Performance, Power, and Area of a High-Speed Dual-Core ARM Cortex-A9‒Based SoC with Clock Concurrent Optimization Technology
Koen Lampaert (Broadcom), Jason Corbisiero

ATC-123 Tues @ 4:10pm
PCIe Gen 3 Implementation on AXI
Raju Pudota

System and Software Design Conference  -- Oct. 31 and Nov. 1, 2012

Exhibit: Cadence booth for these two days is #417. Demonstrations will include the System Development Suite and power-aware signal integrity analysis.

Sponsored Session:  In room #212 Wednesday, Oct. 31, from 11:30 am - 12:30 pm, Cadence will offer a session titled "Prototyping and Early Software Development for ARM-Based Embedded Systems."

Technical Papers:

ATC-218 Wed @ 2:30pm
Improving the Speed and Debug Ability of the Emulation/Prototyping Phase of ARM SoC Development
Leonard Drucker

ATC-303 Thurs @ 10:30am 
Analysis of Software-Driven Power-Management Policies using Functional Virtual Platforms
Michele Petracca

ATC-323 Thurs @ 10:30am 
Fast-Track To Embedded Design With ARM Cortex-M0+ And Cadence Mixed-Signal IC Design Flow
Thomas Ensergueix (ARM), Mladen Nizic

For up-to-date information about Cadence at ARM TechCon, click here. For the ARM TechCon web site and registration information, click here.

Richard Goering




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