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TSMC Forum: An Update on 20nm, 3D-IC, and 16nm FinFETs

Comments(0)Filed under: Industry Insights, ARM, Virtuoso, Encounter, FinFets, IP, PDK, Double Patterning, IC, Liu, collaboration, 28nm, 3DIC, semiconductor, TSMC, 20nm, Segars, 3D-IC, Cadence, wide i/o, ecosystem, 2.5D, foundation IP, FinFET, 64-bit, OIP, 10nm, DPT, CoWoS, Hou, TSMC Forum, Open Innovation Platform, V8, 16nm

TSMC, the world's largest semiconductor foundry, is thinking big when it comes to next-generation process technology. At the TSMC Open Innovation Platform (OIP) Ecosystem Forum Oct. 16, TSMC described reference flows for 20nm and for multi-die integration, and revealed that ARM and TSMC are working on 16nm FinFET technology using ARM's 64-bit V8 processor as a test vehicle.

A common thread underlying all these developments is the early and deep collaboration afforded by the OIP ecosystem, which now includes over 100 partners including EDA vendors, silicon IP providers, and design services houses. Three keynote speakers -- including two from TSMC, and one from ARM -- all spoke of deep collaboration as the key enabling force behind semiconductor technology innovation. "The pace of technology is accelerating, and we know that collaboration is the foundation that's needed to solve the problems that sit in front of us," said Rick Cassidy, president of TSMC North America, in his opening remarks.

Cliff Hou (right), vice president of R&D at TSMC, noted in his keynote that engagements with partners and customers are starting much earlier at 20nm than they did at 40nm. "Through collaboration, we have overcome the challenges of 40nm and 28nm," he said. "Through deeper collaboration and early partnership, I believe we can overcome the challenges of 16nm FinFET solutions also."

Here's what the keynote speakers had to say about 20nm, 3D-IC multi-die integration, and 16nm FinFETs.

20nm is Ready for Design

On Oct. 9, one week before the forum, TSMC announced what calls the first "double patterning aware" foundry reference flow. This 20nm flow includes pre-coloring capability, new RC extraction methodology, double patterning signoff, physical verification, and design for manufacturability (DFM). Subsequently, Cadence announced that TSMC has selected Cadence Encounter and Virtuoso platforms for its 20nm design infrastructure.

"20nm product development is close to complete," said Mark Liu (left), co-chief operating officer at TSMC. "All of the design infrastructure is ready for technology and product development." TSMC's 20nm process uses planar transistors, not FinFETs, "and has less performance gain compared to previous [process node] generations," Liu observed. "However, it offers the industry's highest density, so many customers have already jumped on it." He also noted that TSMC plans to build three 20nm fabs.

"I am happy to announce that our 20nm design solution and IP are available now, so the customer can download all the design kits, tools and packages from TSMC online today," Hou said. The major challenge at 20nm, he noted, is double patterning. Thus, TSMC had to make sure that tools in the reference flow are double-patterning compliant.

The intent is to make things easier for the designer. "Through our collaboration, the 20nm design flow usage is almost the same as the 28nm technology node, so we make the double patterning challenge almost transparent to the customer," Hou said. "Also we provide a methodology for how to effectively handle RC corners for double patterning" (mask shift variation due to double patterning introduces additional corners for verification).

It's not so easy for TSMC. Hou displayed a slide that shows all the items TSMC had to review in order to certify IC routers for compliance with double patterning design rules. It's a long list.

Multi-die Integration with CoWoS

TSMC's chip-on-wafer-on-substrate (CoWoS) process came to light in March with the announcement of an Altera test vehicle developed using this process. Technically, CoWoS is what is called a "2.5D" process, allowing chips to be placed side-by-side on a silicon interposer substrate, but not (yet) allowing full 3D stacking.

On Oct. 9, TSMC announced a CoWoS reference flow, said to be the first that allows multi-die integration in one package. On Oct. 12, TSMC announced the first CoWoS test vehicle using the JEDEC Wide I/O standard. SK Hynix provided the DRAM, Cadence provided the Wide I/O IP, and Cadence and Mentor Graphics provided the EDA tools, according to TSMC. Then, Cadence announced Oct. 15 that TSMC has validated its 3D-IC technology for the CoWoS reference flow.

Earlier this year, Hou said, TSMC demonstrated how to integrate chips using CoWoS technology. Then TSMC extended the CoWoS flow to include Wide I/O DRAM. CoWoS, he said, sets a "foundation for the future," and indeed, TSMC plans to tape out its first "true 3D-IC" test chip, a Wide I/O cube, next year. Hou said that CoWoS is a "very complicated process involving a lot of our partners," but nonetheless, a CoWoS design solution is available for download from TSMC today.

The Next Generation: 16nm FinFET

FinFETs, a new type of non-planar, multi-gate transistor, have attracted much attention in recent months.  In a FinFET, the FET gate wraps around three sides of the transistor's elevated channel, or "fin." This promises greatly reduced power at a given level of performance. (A previous blog post looks at some of the design challenges of FinFETs).

"Once we get into the FinFET transistor structure," Liu said, "Moore's Law will resume its speed, power consumption, and performance trends." He said that FinFETs will be available for design next year with the release of a 0.1 PDK, and the technology will be in risk (early) production towards the end of 2013. He also noted that TSMC is working with ARM on 64-bit processor technology in FinFET.

Compared to the 28 HPM (high performance) process, Liu said, the 16nm FinFET will have about a 40% or 50% speed increase and about a 50% power reduction. TSMC plans to offer a 10nm FinFET by the end of 2015.

Hou said the 0.1 PDK will come out in January, and that one month later TSMC will make its foundation IP available for 16nm FinFETs. This includes standard cells, memories, I/Os, and some specialty IP. The next milestone is the 1.0 PDK release in October, and one month after that TSMC will provide "a complete set of foundation IP" along with standards and interface IP.

Keynote speaker Simon Segars (right), general manager of ARM's Processor and Physical IP divisions, spoke about the ARM-TSMC collaboration on FinFETs. "What we're doing is working together on what the process is going to look like, and trying to anticipate the kinds of chips people will try to build when it reaches mainstream production," he said. "What we're using as a development vehicle is next generation [64-bit V8] ARM processors. We anticipate marrying that with FinFET technology, leading to some very interesting implementations."

"Almost nobody on the planet has experience building chips using FinFETs," Segars said. "So we want to anticipate the issues that will come along. We want to co-optimize the process and the processor. We want to solve issues before our customers encounter them, so they can adopt this technology in a less risky way."

My conclusion: The 20nm and CoWoS reference flows, along with the work on 16nm FinFETs, show that early and deep collaboration can indeed make complex, challenging technologies available to the design community. That's the goal of OIP -- and it appears to be yielding results.

Richard Goering

Photos of Mark Liu and Cliff Hou are from TSMC Ltd.


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