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A New Information Resource for 3D-IC TSV Design

Comments(0)Filed under: Industry Insights, ITRI, TSV, GlobalFoundries, webinar, test, TSMC, 3D IC, 3D-IC, IC/package co-design, Cadence, wide i/o, CoWoS, 3D-IC site

A new solutions page on Cadence.com provides a great deal of information about 3D-ICs with through-silicon vias (TSVs). In addition to a description of the Cadence 3D-IC design, test, and semiconductor IP solutions, it includes press releases, blog posts, whitepapers, articles, and an archived webinar with speakers from Cadence and GLOBALFOUNDRIES.

The page shows how Cadence has been working with customers and ecosystem partners to develop a methodology for 3D-IC design. It explains both the challenges and the Cadence solutions in each of these areas:

  • Design IP, including a Wide I/O offering with memory controller, PHY, and verification IP
  • Implementation support for both digital and custom design
  • Analysis and Verification including parasitics, timing, thermal, and signal integrity
  • IC/Package Co-Design with feasibility planning, connectivity management, and 3D visualization
  • Test, including a DFT architecture and automatic test pattern generation (ATPG)
3D-IC design and verification flow

Two news announcements that occured Oct. 15, 2012 are featured on the site:

TSMC Validates Cadence 3D-IC Technology for its CoWoS Reference Flow

ITRI Tapes Out 3D-IC Chip Using Cadence Technology

The site provides links to a Cadence whitepaper on 3D-IC design challenges and requirements, a technical paper on the Cadence Silicon Realization solution for 3D-ICs, and a number of articles in industry publications.

Finally, the site lists an archived webinar titled "Should You Design Your Next System With 3D TSVs? Hear from GLOBALFOUNDRIES and Cadence." The webinar discusses the design, implementation, and verification challenges of 3D-ICs with TSVs, and demonstrates a production-proven flow. You can access it here.

Richard Goering 

 

 

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