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Si2 Talk: Why System-Level Low Power is Challenging

Comments(0)Filed under: Industry Insights, Palladium, ESL, low power, High-level Synthesis, TLM, UPF, LPC, Si2, CPF, system level, Silicon Integration Initiative, Cadence, low power coalition, firmware, Si2 conference, IEEE 1801, chip planning, Docea, switching activity, architectural modeling, system-level low power, Excel, Pete Hardee, Hardee, power models, SAIF, atomic modeling

There's a lot of interest in "system level" low power design -- but what does it really mean? "There a lot of confusion," said Pete Hardee, director of solutions marketing at Cadence, in a presentation at the recent Silicon Integration Initiative (Si2) Conference. "What's system level, what problem am I trying to solve, and for what purpose am I creating models?"

Hardee's talk was titled System-Level Low Power Requirements - Cadence's Perspective. It was one of a number of talks at the day-long Si2 Conference, which reviewed five technology areas in which Si2 is developing standards. A previous blog post describes a keynote speech given by EDA luminary Jim Hogan on "Custom 2.0" IC design. Cadence and Docea Power sponsored the Oct. 9 conference.

Hardee first reviewed the "realistic scope" of a system, starting at the application software level. "Even if you have great low power techniques, and the firmware can control these correctly, software engineers can still get it wrong at the application level by failing to use the power API correctly," he noted. He also said that chip-level design needs to move up in abstraction so design teams can assess alternative power architectures. "Getting early enough feedback on those architectural decisions can be tough," he said.

Low-Power Design Today

So what are the prevalent low-power methods today? At the firmware level, designers might leverage a previous version of the chip, build prototype boards, or use hardware emulators. At the PCB level, they use design and analysis tools. At the chip level, when considering architectures, "the state of the art is still Microsoft Excel. Customers are still using huge Excel files, trying to model power in 30 different system modes and all combinations of power domain states," Hardee said.

The further up the design chain you are, Hardee noted, the more impactful the decisions you make - and the less accuracy you have. What may be forgotten, however, is that while there's a need for accurate characterization, it may be easier to evaluate representative system activity at a higher level of abstraction. And you may not always need "absolute" numbers (such as, this block burns 250 mW). A "relative" ranking may suffice (this architecture uses 50% more power than that architecture).

Hardee reviewed a number of common low-power techniques, including "macro-architectural techniques" that involve multiple power domains. "These are not techniques you would want to start introducing when you're down at the netlist level, and analyze with a signoff power tool," he noted. "You've got to make some of these decisions a lot earlier than that - so, on what basis are you making those decisions?"

Describing today's "state of the art," Hardee noted that chip planning tools can provide a profile-based power estimation. High-level synthesis can explore micro-architectures for new blocks. The diagram below shows a present-day low power flow from Cadence. It includes chip planning, power estimation and optimization with high-level synthesis, and power-aware emulation with the Palladium XP system. This flow can help designers get to RTL quickly.

How Can We Get Higher?

System-level power modeling is not rocket science. The power of a block basically depends on voltage, frequency, and the state. A high-level model can evaluate, for example, the impact of cache misses on different memory transactions. But there's a problem, Hardee said -- the availability of models and the effort of creating the models. And even if you have models, configuration and realistic annotation are challenging.

Hardee discussed the work that the Si2 Low Power Coalition (LPC) is doing in atomic modeling. This is the ability to model an IP block's power characteristics accurately and completely without requiring a gate level or RTL description. Atomic models will be useful, but Hardee cautioned that "one size does not fit all. In ESL [electronic system level] there are very different abstraction levels and that definitely affects the power, energy, and accuracy." A good bet for block-level power, he said, is the approximately timed (AT) level of the SystemC transaction-level modeling (TLM 2.0) standard.

Finally, Hardee noted that models are not very useful without activity. One bit of "low hanging fruit" may be expanding the IEEE Switching Activity Interchange Format (SAIF) to TLM. Fortunately, both the Common Power Format (CPF) and IEEE 1801 Universal Power Format should be able to describe power domains, states, and system modes with little modification.

There were two other presentations about low-power standards at the Si2 Conference. In one, Rhett Davis of Northern Carolina State University spoke about describing power models in the Liberty format. In another, Woody Norwood of Apache Design (now part of Ansys) talked about his company's Power Artist analysis product and its use of OpenAccess and CPF. Other topics at the conference included design for manufacturability (DFM), process design kits (PDKs), 3D-ICs, and OpenAccess.

Richard Goering



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