Real number modeling (RNM) provides a fast way to run a chip-level simulation with analog values, but support for it in the current SystemVerilog Language Reference Manual (2009 LRM) is very limited. A recently archived webinar shows how the next SystemVerilog LRM (which may be dated 2012 or 2013) offers new features that support RNM. It also shows how to write Verilog-AMS real-number models today that can be reused later in SystemVerilog.
Titled "Is SystemVerilog the Future of Mixed-Signal Modeling," the webinar was given by Dan Romaine, mixed-signal solutions engineer at Cadence. In the webinar, Romaine reviewed behavioral modeling choices, discussed the benefits of RNM, described support for RNM in various languages, presented additions to SystemVerilog 2012/2013 that will provide strong support for RNM, and showed how to write Verilog-AMS models for compatibility with SystemVerilog.
Romaine cited the growing amount of analog circuitry on today's SoCs, and noted that isolated analog and digital verification is no longer enough to reach tapeout. What's also needed is a chip-level functional verification that looks at the functional interactions between analog and digital blocks. But how to do it, given that a SPICE/RTL co-simulation would be much too slow?
One answer, Romaine argued, is real number modeling. This is a signal-flow based approach that uses real (floating-point, continuous) values to represent current or voltage in discrete time. It runs in a digital simulation environment and removes the need to use a much slower analog solver. In addition to allowing digital simulation speeds, RNM lets designers use digital verification techniques such as assertions, coverage, and metric-driven verification.
Romaine showed an example that compared transistor-level and RNM simulation times for a 14-bit ADC and DAC, which required 16,384 steps (2**14) for simulation. Transistor-level simulation took several days. RNM simulation took 3 seconds. This is an internal example from Cadence; Romaine also cited RNM testimonials from several customers.
RNM performance case study
Romaine then discussed the pros and cons of various modeling languages, focusing on their RNM support. Verilog, for instance, has very limited RNM support; you can use real variables inside a model, but there are no real variable ports. VHDL, on the other hand, supports real number ports, has custom/compound signals and ports that make it possible to pass both current and voltage, and offers custom resolution functions. The catch, of course, is that Verilog is far more widely used for digital design than VHDL.
Verilog-AMS is widely used for RNM. It supports real number ports and variables, along with 6 resolution functions on wreal nets. It has an analog solver if you need the accuracy, along with a discrete solver that can be used for real value equations. Cadence has developed and proposed some extensions to the Verilog-AMS wreal data type.
SystemVerilog, meanwhile, is making strong inroads into digital design and verification. Far more than just another version of Verilog, it also includes extensive verification features and an assertion language. But the 2009 LRM does very little for analog modeling. The upcoming 2012-2013 LRM, Romaine said, does far more. He previewed these features:
- User-defined types that can hold one or more real values (such as voltage, current, impedance) in a single complex datatype that can be sent over a wire
- User-defined resolution function that specifies how to combine user defined types
- Type-less interconnects between nets and ports, allowing an interconnect to assume a type based on what it's connected to
Romaine said these changes will appear in the next SystemVerilog LRM, which may be titled 2012 or 2013 based on when it's officially ratified. Cadence will implement these features, he noted. Romaine showed the following chart, which offers a good summary of the modeling features offered by various languages:
Modeling feature chart
If You Can't Wait
But what if you want to do some real-number modeling today? "What we're finding is that many customers who want to use the new SystemVerilog syntax are not willing to wait for it to be released," Romaine said. Therefore, Cadence has created a reusable way to write Verilog-AMS models that can be ported to SystemVerilog in the future. The trick is to avoid domains and disciplines, which exist in Verilog-AMS but not in SystemVerilog.
Therefore, Cadence has created six new "discipline less" wreal nets that combine resolution functions with data types - for example, wrealmin, wrealsum, and wrealavg. Romaine provided a code example showing how this is done. Once the new SystemVerilog LRM is implemented, these portable Verilog-AMS models can become SystemVerilog models. You'll just need to rename the file extension, and import a SystemVerilog wreal type package, which will be provided by Cadence.
So is SystemVerilog the future of mixed-signal modeling? It depends, Romaine said, on your background (analog or digital?) and what you're trying to achieve. Meanwhile, he emphasized, Cadence will continue to support wreal modeling with Verilog-AMS. This point was also made at a panel discussion at the Mixed-Signal Technology Summit held at Cadence Sept. 20, where there was a lively discussion about wreal, Verilog-AMS, and SystemVerilog.
Cadence Community members can access the free webinar here (quick and free registration if you're not a member). Cadence customers can read an app note here that shows how to write Verilog-AMS models that will be portable to SystemVerilog.