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Panel: Mixed-Signal Designers Reveal “Gaps” and Solutions

Comments(0)Filed under: Industry Insights, Virtuoso, CPF, Analog, Mixed-Signal, mixed signal, Panel, broadcom, AMS, ADE, UVM, TI, SystemVerilog, assertions, analog/mixed-signal, 20nm, Sikand, IC Manage, UVM-MS, behavioral modeling, wreal, PSL, real number modeling, Khan, Maxim, mixed-signal summit, AMSmadeEZ, OSS, Shah, closing the gap, Meier, Chizmadia

Are we closing the gaps in mixed-signal design? That question was posed to five panelists, including three Cadence customer representatives, at the Mixed-Signal Technology Summit held at Cadence Sept. 20, 2012. While panelists noted progress in mixed-signal design tools and flows, they pointed to a number of rough spots that still need work.

The panel came at the end of a day-long session that included two keynote speeches and a number of presentations from Cadence executives, customers, and partners. I had the honor of moderating the panel. Panelists were as follows, listed as they appear from left to right in the photo below:

  • Bob Chizmadia, services director, AMS Methodology Services team, Cadence
  • Neyaz Khan, distinguished member of technical staff, Maxim Integrated Products
  • Nishant Shah, verification engineer, Broadcom
  • Shiv Sikand, vice president of engineering, IC Manage
  • Bill Meier, senior methodology engineer, Design Automation group, Texas Instruments

Panelists first gave brief presentations on the work they're doing and the gaps they've encountered. Following are some of the highlights.

Neyaz Khan - Mixed Abstractions

Khan is part of a team at Maxim that's responsible for verification across the company. One challenge is the "abstraction problem" that results from combining analog and digital models at different levels of abstraction. He would like to be able to create a single testbench and change the block abstraction level at any given time. Such a testbench would probably be based on the Universal Verification Methodology (UVM), and would require people with advanced digital verification skills.

One current problem with real number modeling, Khan noted, is that "you can reference an analog quantity in a single floating-point number that represents a wire, and that's great. But it also has some limitations. You can either pass current or voltage but you can't pass both." As a result, engineers may need to go to lower levels of abstraction.

Nishant Shah - Behavioral Models

Shah's group at Broadcom works on behavioral models of analog designs, verification of behavioral models against schematics, and the setup flow for top-to-bottom verification coverage. He noted that the initial setup time for analog/mixed signal (AMS) verification is high, SystemVerilog with AMS is not fully supported, and that AMS connect modules need more enhancements.

Shiv Sikand - Design Management

Sikand is founder of IC Manage, a Cadence partner and provider of design data management tools. He noted that analog/mixed-signal designers are facing increasing complexity, and are working in dynamic environments. "You want to continually deal with change and manage that change so you don't have surprises at the end," he said.

With respect to design management, Sikand said customers are challenged in four key areas:

  • Internal IP reuse - requires change management and knowledge sharing across design teams.
  • SoC assembly - top-down assembly method is needed to capture design dependencies.
  • Network storage bottlenecks - name spaces need to be globally consistent rather than tied to a local site. EDA tool acceleration is needed.
  • Bug management - requires bug dependency tracing and notification, and bug fix preparation.

Bill Meier - AMS Gaps

Meier is project lead for AMSmadeEZ, a TI initiative intended to make AMS design easier for the analog engineer. Rather than talking about AMSmadeEZ, however, Meier listed a number of things that make AMS design difficult.

Meier first noted that most analog engineers prefer to stick with the Virtuoso Analog Design Environment (ADE) and avoid digital tools. AMS-OSS (Open Simulation System) works well for fairly simple SPICE and Verilog designs. Multi-language design needs more support. Standard Delay Format (SDF) annotation is a pain point - it can be difficult to keep SDF files aligned with the correct version of the gate netlist.

Assertions may come from many sources - Spectre, SystemVerilog, Property Specification Language (PSL), e language, and more - but there is "no one type of assertion that works throughout the entire flow for all simulators," Meier said. He pointed to some limitations in the Common Power Format (CPF) with respect to supply-sensitive connect modules, tracking electrical voltages, and insertion into RTL and gate-level netlists. Finally, like Khan, he called for the ability to pass multi-value data for real number modeling.

Bob Chizmadia - Advanced Node Challenges

"Are we closing the gap? I actually think we have," Chizmadia said. He pointed to real number modeling, metric-driven verification, assertion-based verification, and other techniques that weren't previously available for AMS verification. Another big advantage is an interoperable analog and digital design flow. Now, he noted, engineers can use the best tool for the job, moving over to the Encounter Digital Implementation System, for example, if there are too many pins to floorplan in Virtuoso.

However, advanced nodes (22nm and below) remain challenging for mixed-signal design. "The challenges in physical implementation are daunting," he said. "There's an explosion in design rules. You can't just use the same techniques you used before -- you have to come up with some automation."

Questions and Answers

Q: Is there a need for a dedicated team for mixed-signal verification?

Khan: Yes, it helps to have a separate team, and that's what we do at Maxim. One advantage is that we can develop IP that the whole company can use. Secondly, we can leverage what we do across the company. Also, when you bring in advanced techniques, it helps to come from a centralized team so it spreads in a uniform way.

Q: From the presentations today I see there is duplicated effort in every company. Is that the way forward? Does everyone have to figure these things out on their own?

Khan: In verification, Cadence has done a wonderful job in bringing UVM out with the other vendors. UVM-MS was created at Cadence to take techniques from the digital side and extend them into analog. It involves things like an executable verification plan, collecting coverage, and writing assertions that go across analog and digital. I think there's a pretty strong effort to make it a standard. The question is how fast it will be adopted.

Chizmadia: One thing about standardizing anything is that you have to remember that every company has a unique design. I think you need a lot of flexibility in how you're going to do verification.

Q: You have different power domains on your chip that are going to be on and off at different times. That spawns a whole new breed of bugs that will require new methods to detect. Do you have some methodologies you're willing to share? And what is your experience with CPF?

Khan: CPF has done a pretty good job on the digital side. In the mixed-signal environment the picture gets very different. You can do everything right with analog, and everything looks great with digital, and you bring analog and digital on the chip together and all hell breaks loose. Cadence has introduced some new things. You can, for example, create a macromodel of the CPF from within the analog environment. That can help because you now have some visibility at the top level.

Q: We are using AMS and wreal models. We hear this will be moved to SystemVerilog. What's the migration path and what's the schedule?

Shah: We have been using wreal models and they work well with SystemVerilog. So far we haven't encountered any model that doesn't work with SystemVerilog, if it follows the LRM [Language Reference Manual] syntax.

Cadence R&D Rep: We will continue to support Verilog-AMS and you will be able to run all your Verilog-AMS wreals with SystemVerilog. Nobody is forced to use SystemVerilog. When you go to SystemVerilog, it will be able to hold multiple real values.

Q: What training should universities provide for verification engineers and behavioral modeling engineers? Do you think we need that?

Shah: I didn't have any experience from universities in India. I had to learn what I picked up on the fly from AEs. But having the training in the university before we get to industry is a plus. That's because you have already spent time getting used to the tool, and now you can spend your time designing something.

Richard Goering

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Keynote: From "Tribulations" to Mixed-Signal Success at Texas Instruments

 

 

 

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