Got a few picoseconds to spare? If you're a PCB designer working with a multi-Gbit/second serial link interface such as PCI Express 3.0 or a DDR memory interface, maybe not. Two new features in the Cadence Allegro 16.6 PCB design solution - announced today (Sept. 25, 2012) at PCB West - aim to help board designers achieve timing closure and optimize layouts for high-speed signals.
There are actually a number of new features in Allegro 16.6, including team collaboration using Microsoft SharePoint, ECAD/MCAD co-design, and expanded support for embedded components. There's also a companion OrCAD 16.6 release that includes a new signal integrity flow and improvements to the PSpice simulator. In this blog post, however, I'll focus on two new additions to the Allegro High-Speed Option - integration with the EMA Timing Designer product and the new Auto-interactive Delay Tune (AiDT) technology.
In brief, Timing Designer and AiDT are part of a new flow (depicted below) that accelerates timing closure on high-speed signals. As before, the Allegro PCB SI tool provides a pre-layout analysis to help designers develop constraints. Now, however, designers can pass interconnect delays to Timing Designer, use that product to analyze setup and hold margins, and pass the resulting timing constraints to the Allegro PCB Editor. Here, designers can use AiDT to "tune" layouts to meet delay constraints, and Allegro can provide timing-aware physical implementation.
A Venerable EDA Product
If Timing Designer sounds familiar, that's not surprising - it's among the most venerable of EDA products, having originated with a company called Chronology over 20 years ago. Today it's offered by EMA Design Automation, which also distributes OrCAD products. Timing Designer today is an interactive timing analysis tool aimed at high-speed, multi-frequency designs. The EMA Timing Designer web site lists these features:
- Easy-to-use timing diagram editor enables rapid specification of design requirements
- Dynamically linked timing spreadsheet for accurate modeling of complex delay and constraint effects
- Powerful timing analysis engine quickly identifies worst-case timing margins
- Instant updates of intelligent timing diagrams support quick evaluation of design alternatives
- Robust project manager
- Extensive import/export support
A free trial is available from EMA.
What is new is the integration of Timing Designer with Allegro PCB SI. Timing Designer "allows you to figure out the setup and hold times that are required, for example, if you want to make sure a strobe arrives at the same time data arrives," said Hemant Shah, product marketing director at Cadence. "It tells you what margins you need so you can meet the timing. Then AiDT can take the constraints and quickly adjust the routes."
AiDT is an "auto-interactive" way to tune the PCB layout to meet timing constraints. You could do the same thing manually, one signal at a time - but AiDT will automate that process and allow you to select a group of signals, or even an entire interface. It will then adjust the traces automatically based on your constraints. But you decide which signals to optimize in which order. According to Shah, AiDT will always meet timing constraints provided board space is available. AiDT will benefit from, but does not require, the use of Timing Designer.
AiDT allows some choices. You can decide, for instance, whether you want accordion or trombone topologies for traces, and you can define the miter size of corners. According to Shah, early customer experience suggests that AiDT can shorten the overall time to tune high-speed signals by 30 to 50%.
To me, AiDT sounds a bit like synthesis in the IC design world. You feed constraints into a tool and it optimizes and tunes your design. In effect, you're working at a higher level of abstraction with AiDT, because you don't have to manually tune every individual signal. If you look at a given group of signals, Shah said, AiDT might be able to accomplish in 5 minutes what would take a designer half a day.
So What Else is New?
Here's a quick rundown of what else is new in the Allegro 16.6 release:
- The first collaborative PCB design environment using Microsoft SharePoint. This works with Cadence Allegro design authoring and PCB implementation tools, and unlike most product lifecycle management (PLM) or data management systems, it allows version control at the block level. Further, most customers already have SharePoint in house.
- Support for embedded components that have dual sided contacts and are inserted vertically.
- A streamlined PCB Team Design option with increased flexibility to move components or routes across partition boundaries as well as allow editing of constraints inside a partition.
- Collaboration with NVidia to improve display performance for GPUs that can cache OpenGL code.
- PCB/enclosure co-design through an ECAD-MCAD flow based on EDMD schema version 2.0, a proStep iViP standard.
Allegro 16.6 PCB solutions will be available Q4 2012. You'll find more information here about Allegro 16.6 and here about OrCAD 16.6.
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