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MemCon Keynote: Cloud, Mobility Disrupt Semiconductor Memory Ecosystem

Comments(0)Filed under: Industry Insights, Micron, Verification IP, VIP, cloud, Denali, memory, DDR, MemCon, MRAM, PCM, TSMC, Cadence, storage, DDR4, SRAM, keynote, semiconductor IP, latency, bandwidth, design IP, interconnect, Martin Lund, Lund, DDR4 IP, mobility, compute, 28HP, hybrid memory cube

Do you think memory is a boring, slow-moving technology? That's definitely not the case, according to Martin Lund (right), senior vice president at Cadence and keynote speaker at the MemCon 2012 conference Sept. 18, 2012. Lund asserted that these are "exciting times" for a semiconductor memory ecosystem that is being rapidly reshaped by the mobility and cloud computer revolutions.

Part of what's exciting is the reappearance of MemCon, which was organized for nine years by Denali Software and which became the memory industry's premier conference. Cadence acquired Denali in 2010. After a brief hiatus, MemCon is back - and this year's free, one-day conference included three thought-provoking keynotes, a panel on the future of memory, two tracks of breakout sessions, exhibits, and breakfast and lunch.

A former Broadcom executive, Lund joined Cadence in early 2012 as senior vice president of R&D for the SoC Realization Group (a recent Q&A interview tells more). He brings both a user and semiconductor IP provider perspective to the memory market, which he believes is undergoing a period of dynamic change. "The cloud revolution is really fueled by the mobile revolution, and all those cell phones and tablets out there are driving the need for the cloud infrastructure," Lund said. "That's enabling people to download videos, do texting, use Facebook - and all that data has to be stored somewhere. It's not stopping any time soon - it's accelerating."

Compute, Interconnect, Storage - Three Legged Stool

The cloud is challenging memory technologies in three directions, Lund noted - compute, interconnect, and storage. In the compute area, the priority is higher performance and greater memory capacity. Interconnect is driven by the need for higher bandwidth, and storage requires lower latency and higher IOPs. "These are three legs of a stool," Lund said. "If one gets too short we can't keep moving forward like we have in the past."

The demand for higher performance is accelerating faster than memory standards such as DDR2, DDR3 and DDR4, Lund said. This opens an opportunity for engineers to find ways to get more out of memories, and provides an incentive to develop new technologies. One proposed way to get around the memory bottleneck, he noted, is the Micron hybrid memory cube, which was the topic of a second MemCon 2012 keynote.

As he discussed the need for higher bandwidth interconnect, Lund related his experience at Broadcom, where engineers initially solved problems by putting SRAM on chip. But the time came when they couldn't put enough SRAM on the chip and couldn't go outside the chip, because there was no memory interface that was fast enough. Thus, even with SRAM on chip, designers can quickly run out of bandwidth.

To improve storage, designers must "hide the latency," Lund said. "Latency is the key to your GHz CPUs," he said. "Without low latency, GHz CPUs will be sitting around doing nothing for a long time." He presented an interesting analogy. DDR latency is 13.5ns, about the time it takes light to travel across a room. NAND Flash latency is 50K ns, about the time it takes light to travel from San Jose to Cupertino (15km). Disk latency is 10M ns, about the time it takes light to travel from San Jose to Chicago (3,000km).

Why memory latency is crucial 

Go Pound Sand

Memory economics are always challenging, Lund said. He noted that it now costs $10 billion to build a memory fab. What you get out if it is memory that sells for less than a dollar per billion bits. Semiconductors are made out of sand, and the billion-bit equivalent of sand costs $25. "So you make something, put it through a fab that costs $10 billion, and it becomes cheaper. It's an interesting phenomenon."

However, Lund noted, new memory technologies are emerging that might solve enough problems so that people will "pay a little bit more per bit." These include 2.5D and 3D-ICs, phase-change memory (PCM), magnetic RAM (MRAM), and others.

Further, the memory ecosystem is "coming together." This ecosystem includes memory manufacturers, standards bodies, systems houses, and packaging and manufacturing providers. It also includes semiconductor IP providers, which is where Cadence comes in. It's a challenging business. "It's not just about putting out a memory controller and asking you to use it - it's about collaborating across the industry to solve real problems about manufacturability and performance optimization," Lund said.

He noted that Cadence provides 6,000 memory models supporting 85 memory manufacturers, has had thousands of designs verified by verification IP, has delivered 3,100 customized controllers, and is the first commercial provider of DDR4, LPDDR3 and wide I/O controllers and PHYs. "This is not a job shop. This is not one size fits all. Every SoC is different, and there will always be a need for differentiation," Lund said.

Lund's parting words: "It's time for us to get some excitement back into the memory industry. Sure CPUs get more airplay and maybe even flash, but memory is like oxygen - everybody needs it and it had better be there when you need it, at the right latency and the right time."

Addenda: Proven in Silicon

Silicon IP may be software, but on the exhibit floor, Cadence brought some real silicon to the party. Several weeks ago Cadence announced the industry's first DDR4 design IP solutions proven in 28nm silicon. This included a test chip manufactured in TSMC's 28HP process technology, and the test chip was in the Cadence booth as part of a DDR4 IP demo, as shown in the photo below.

Brett Murdock (left) and Marc Greenberg, both of Cadence, and the 28nm test chip

More to come on MemCon 2012!

Richard Goering

 

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