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Free UVM Tutorial Boosts IC Functional Verification Skills

Comments(0)Filed under: DVCon, SystemC, TLM, Accellera, OVM, verification, Functional Verification, UVM, Cadence, Mentor, Synopsys, register package, video, testbench, Accellera Systems Initiative, sequences, Doulos, Factory, UVC, UVM tutorial, base classes, communication, Universal Verification Methodology

Whether you're new to the Universal Verification Methodology (UVM) or an experienced user who wants to know more, a free on-line tutorial will help you improve your IC verification skills. The half-day tutorial, titled "UVM: Ready, Set, Deploy!" is available through the Accellera Systems Initiative, and it is a videotaped version of a tutorial given at the DVCon conference earlier this year.

The tutorial starts with presentations from verification experts at Mentor Graphics, Doulos, Cadence, and Synopsys. These four presentations provide an in-depth introduction to UVM, and they explore such topics as a structured verification methodology, base classes, resource configuration management, error handling, report generation, and the UVM register package. These presentations are followed by four user experience presentations.

While the whole tutorial is over four hours long, you can listen to any of the 8 presentations individually. You'll see a video of the presenter along with his or her slides. Navigation is easy - you can scroll up and down in a menu to go forward, or go back to, a given slide. At the end of each presentation, you'll be offered the opportunity to download slides. To access the tutorial, you can register here, and you can then select any of the following presentations:

Part 1: Base Classes in UVM
Tom Fitzpatrick, Mentor Graphics
40 min.

Part 2: Communication and Sequences
John Aynsley, Doulos
38 min.

Part 3: Customizing Your UVM Environment
Kathleen Meade, Cadence
32 min.

Part 4: Register Modeling in UVM
Adiel Khan, Synopsys
30 min.

User Experience 1: Getting Started with UVM
Vanessa Cooper, Verilab
33 min.

User Experience 2: Stacking Verification Components in UVM
Peter J. D'Antonio, The MITRE Corp.
Stephen D'Onofrio, Paradigm Works
30 min.

User Experience 3: OVM to UVM Transition
John Fowler, AMD
Justin Refice, AMD
35 min.

User Experience 4: VC Building Blocks with UVM
Mark Strickland, Cisco Systems
43 min.

Here are brief reviews of the first four parts.

Part 1: Base Classes in UVM

Tom Fitzpatrick, verification evangelist at Mentor Graphics, discusses the rationale for UVM and explains how it offers "freedom from choice" through a common language and strategy. He discusses key concepts such as the separation of tests from testbenches. He shows how to build a UVM environment, architect a UVM testbench, and use Universal Verification Component (UVC) building blocks. He discusses the status of run-time phasing and notes what's available now.

Part 2: Communication and Sequences

John Aynsley, CTO of training firm Doulos, first discusses transaction-level modeling (TLM) communications in UVM. He shows how it allows message passing in UVM by making method calls, such as put, get, and peek, through ports and exports. Secondly, he describes sequencer-to-driver communications, showing how sequences run on sequencers and communicate transactions to drivers. Finally, he talks about "structuring sequences," noting how UVM makes it possible to build test sequences out of other sequences.

Part 3: Customizing Your UVM Environment

A key attribute of UVM components, says Kathleen Meade, verification solutions architect at Cadence, is the ability to configure them "from above" without having to go in and rewrite a lot of code. She focuses on UVM facilities for customization in five areas: Configuration, Factory, Messaging, Callbacks, and Command-Line Processor. She shows how to configure a testbench, define stimulus for a test, and use the UVM Configuration Database. She shows how the Factory provides a central location for creating class instances and objects of registered types. Meade also explains how to customize messages, how to use callbacks to add functionality to existing components, and how to use command-line arguments to modify UVM behavior.

Part 4: Register Modeling in UVM

This presentation by Adiel Khan, verification expert at Synopsys, is divided into two sections. The first section provides information about the UVM register package and how it's structured. The second section shows how the register package is used with the device under test (DUT). It covers integration steps, instantiating a register model, bus adapters, implicit and explicit monitoring, resetting the register model, predefined functionality methods and sequences, read/write API, and user-defined sequences.

The "UVM: Ready, Set, Deploy!" tutorial is sponsored by ARM, Cadence, CircuitSutra, Forte Design Systems, Mentor Graphics, and Synopsys. Again, you can access it here. Videos are also available for DVCon 2012 presentations on SystemC, UCIS, and IP-XACT.

Richard Goering

 

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