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Digital Logic in Analog Block – How Will You Test It?

Comments(4)Filed under: Virtuoso, RTL Compiler, Analog, DFT, Mixed-Signal, mixed signal, ATPG, synthesis, test, digital, IEEE 1500, MBIST, design for test, BIST, Petrakis, IC test, scan chains, control logic, Melchiorre, mixed-signal test, Virtuoso Digital Implementation, VDI, analog test

Analog IP blocks these days have increasing amounts of digital control logic. With very small amounts of digital logic, it's possible to just draw gates on the schematic and run targeted tests that will hopefully catch any errors. But when you have several thousand digital gates, a new approach is needed, as I discovered in a recent discussion.

"2,000 gates is probably a good transition point where people switch from manually inserting gates in a schematic to synthesis," said Bob Melchiorre, director of field operations for digital implementation at Cadence. "Beyond 2,000 gates you have to start thinking about how you're going to test it, because you cannot guarantee that simulation or targeted testing will catch all the issues. Around 10,000 gates it starts getting completely unbearable, and you cannot write enough targeted tests to find all the faults in your digital logic."

As a result, Melchiorre said, analog designers have to start thinking about design for test (DFT) insertion and automatic test pattern generation (ATPG), which are concepts that analog designers never had to think about in the past. "It's a scary thing," he said. "Heads start popping in the analog community."

There are basically two approaches to testing a digital block within an analog/mixed-signal design. One approach is to capture functional patterns and hope for good coverage. One typical problem, as shown in the diagram to the right, is that not all digital block pins can be controlled or observed by the tester. However, faults must be stimulated and observed by tester pins in order to be found.

The second, and preferred approach, is to use structured test on the digital block. This starts with the insertion of a test architecture that makes it possible to access the digital logic block. While you could add a number of pins that peek into the digital block, this is an expensive solution. A better approach is to instantiate a scan chain that can be tested through a JTAG port. Most scan chains can share existing control pins. Following scan chain insertion, you need to generate high-coverage test vectors, and the easiest way to do that is with ATPG.

Using Synthesis

Probably the main argument for using synthesis is that without it, you will have to manually instantiate every gate on the schematic. Also, a synthesis-based flow makes it easier to modify the design for derivative products, or to port it to another process technology.

From a DFT standpoint, synthesis automates scan chain insertion. You can manually build a scan chain, but this is a painful process, according to Bassilios Petrakis, product marketing director for DFT at Cadence. "During synthesis we not only know how to insert things, we also know how to connect them," he said. "We can connect based on timing, physical awareness, or power domains."

In addition to scan chains, the Cadence RTL Compiler can also handle DFT insertion for compression logic, test points, boundary scan, IEEE 1500 core wrappers, memory built-in self test (MBIST) and logic BIST (LBIST).  Some of these techniques are also useful for analog/mixed-signal test. SerDes designers, for instance, often use LBIST, Petrakis said.

If you use the Cadence Virtuoso custom/analog design system, the most cost-effective way to add a synthesis capability is with the Virtuoso Digital Implementation (VDI) product shown in the diagram below. VDI is essentially a capacity-limited version of the Encounter Digital Implementation System and RTL Compiler. It makes analog and digital co-design possible using the OpenAccess database.

VDI does not include ATPG, but that is a capability you will want to consider when digital blocks approach 10,000 gates. ATPG can automatically generate high-coverage test vectors. Otherwise designers use simulation, but this doesn't guarantee coverage, Melchiorre noted. Without ATPG, he said, "you can't guarantee that faults will be caught."

The Encounter Test product line offers ATPG with compression to reduce test time. The Cadence flow automatically generates testbenches to validate test patterns in simulation. Melchiorre noted that simulation of the automatically generated test patterns provides a measure of test coverage -- a critical parameter for reducing field returns and providing end customers with high-quality silicon. This is of vital importance in medical and automotive market segments.

"There is a mystique in the analog world around DFT and ATPG," Melchiorre said. "Analog designers don't want to deal with it - they feel it's out of their realm. They do need to worry about it - but we'll make it easier."

Richard Goering



By Harry Chen on September 11, 2012
From my experience with mostly-A-some-D designs, there isn't enough digital I/O pins to support more than one external scan chain. So designer should consider some kind of serialization and compression scheme to support multiple internal scan chains in order to reduce scan testing time. Also to achieve high fault coverage of the digital blocks,control/observe  test points should be inserted in the analog/digital interfaces.

By Bassilios Petrakis on September 12, 2012
Hi Harry, Thanks for posting your comments.  Indeed in mostly A and some D designs, there isn't enough digital I/O pins to support more than one external scan chain. We do offer in Encounter Test a low pin count test solution that does exactly what your are refering to -serialization of scan plus compression scheme. It is called "SmartScan".  With reference to high fault coverage achievement, we recommend complete isolation of the digital portion of the design using IEEE1500 core wrapper together with strategic test points inserted to improve observability and controllability. Insertion of these structures is automated in the RTL Compiler/DFT Architect cockpit.

By Nila on September 12, 2012
It is interesting. It reminds me my  years working at Telecruz Technology, and recent college class work.

By Robert Melchiorre on September 14, 2012
Harry,  thanks for your comment.  You're right.  At the top level of the design it is hard to dedicate pins for testability, and they are usually shared with functional pins and selected by a mode pin.  One scan chain for 10K gates should be enough, don't you think?  At what point (how many gates) have you found that multiple scan chains are needed?  How about compression?  It is a function of ATE memory capacity and test time atlhough it adds additional logic - so it's a trade off.

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