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Panel: Signal Integrity Solutions for High Data Rate Interfaces

Comments(0)Filed under: Industry Insights, Panel, NXP, PCB, memory, DDR, signal integrity, SI, Cadence, DDR4, PCI Express, PDN, DDR3, IBIS, power analysis, PCIe, USB, crosstalk, USB 3.0, power delivery network, PI, webinar:, interconnects, 3G SDI, voltage swing, Nadolny, FEXT, signal integrity analysis, IO, Samtec, SI analysis, NEXT, I/O, Griffen, Gbit/second, Tung, ISI, high data rate, eye diagrams, interfaces, Bogatin, equalization, connectors

Serial link and DDR memory interfaces are well into Gbits/second territory, making it possible to design a new generation of high-performance devices. But these new interfaces can also greatly increase signal integrity challenges. At an August 28 EDN-hosted webinar panel, experts provided a wealth of practical information about signal integrity challenges and solutions at high data rates.

The webinar was sponsored by Anritsu, Cadence, NXP, and Samtec. It was moderated by Eric Bogatin, signal integrity evangelist, Bogatin Enterprises. Panelists were as follows:

  • Allen Tung, applications engineer, NXP Semiconductors
  • Brad Griffin, product marketing director, Cadence
  • Jim Nadolny, senior signal integrity and EMI engineer, Samtec

Bogatin opened the webinar by pointing to multi-Gbit/second interfaces like serial ATA, PCI Express (PCIe), USB 3.0, Infiniband, and Gigabit Ethernet. "There are two kinds of engineers - those who have signal integrity problems, and those who will," he said. "As data rates increase, signal integrity problems increase, and luck decreases. In a gigabit-per-second scheme, luck and hope can't be part of the design strategy."

The panel proceeded on a question-and-answer basis. Here are the opening questions and some responses.

Q1: What are the interface transitions your customers are working on, and what are examples of the signal integrity challenges created when data rates increase?

Tung: USB 3.0 is very different from USB 2.0. USB 3.0 bit rates (at 5 GBits/second) are 10X faster, signal swing level is 1V compared to 3V, and cable length is reduced to 3 meters from 5 meters. "If you follow the reference design guidelines, you should be able to guarantee the USB 3.0 subsystem will work properly, but in reality the problem is more complicated." Tung explained that today the USB 3.0 host controller is usually integrated into a chipset, which could be located anywhere on the motherboard. Depending on the size of the motherboard and the location of the controller and external connectors, the total route length could be longer than what is specified in USB 3.0 design guidelines.

Nadolny: 3G SDI is a 75 ohm digital video spec for 1080p video at 3 Gbits/second. While 50 ohm BNC connectors were often used to increase bandwidth in analog video, 3G SDI requires true 75 ohm BNC connectors. The PCB and connectors have fairly high isolation requirements, and maintaining 60-80 dB of isolation through them is a major design challenge.

Griffin:  In addition to serial link interfaces, DDR memory interfaces are in the Gbit/second range too. With memory interfaces, the challenge is meeting timing. One way these interfaces run faster is by reducing the voltage swing as signals transition. With DDR3, the voltage swing is 1.5V; with DDR4 it will be as low as 1.05V. "You have to look at your signals in the context of power and ground because voltage instability will push timing in or out, and potentially cause setup and hold violations you haven't seen before."

Q2: We can't use luck and hope any more as part of our design strategy. Can you offer some examples of the new design strategies we might want to consider?

Nadolny: "We're a connector company, so we help customers come up with intelligent pin mapping." Example: PCIe Gen3 uses a dual-simplex communication channel with dedicated transmit and receive lines. Far-end crosstalk (FEXT) attenuates with length, but near-end crosstalk (NEXT) does not. You can avoid NEXT problems by isolating transmit from receive pins in the connector pin mapping. Nadolny showed an example of how this is done.

Griffin: "We encourage customers to look at power and signal integrity early and throughout the entire design process." With Cadence tools, designers can do some pre-route analysis to develop constraints that can be applied to the PCB design. Designers can capture both electrical and physical rules, and check them by running analysis throughout the design process. As shown in the following slide, designers can also configure their power delivery network (PDN) and make sure it can return signals efficiently.


Tung: Three types of signal conditioners can help with signal integrity. These are re-drivers, re-timers, and repeaters. Signal conditioners include a receiver equalizer and line driver, and have an equalization capability that can boost the eye opening of an incoming signal. The re-driver is the cheapest, but has limited ability to reduce inter-symbol interference (ISI) and can't reduce random or deterministic jitter. The re-timer can reduce these types of jitter but is more costly. The repeater provides the best signal integrity improvement but costs the most.

Q3: Are there any general design guidelines or rules of thumb you can offer, from your experiences, which will give designers a rough idea of specific design changes to consider?

Griffin: "We've come to the conclusion that where we are today with multi-gigabit interfaces, rules of thumb are not going to cut it anymore. We're encouraging our customers to get involved with early analysis." With signal integrity analysis, the two main issues are modeling I/O buffers and modeling interconnects. To model I/Os, you could use IBIS models or transistor-level models, or create your own. "Just use the best data available and do a pre-route analysis and drive those constraints into the system. Then follow up with a detailed analysis at the end of the design process."

Tung: One thing designers can look at is attenuation from traces, vias, connectors, and cables. Fine-tuning the transmitters' de-emphasis and receivers' equalizer settings usually helps improve signal integrity. NXP builds test boards that contain different trace lengths, and may be manufactured with different impedance parameters. They use an oscilloscope eye diagram to find the best setting for transmitter de-emphasis, and a signal generator to evaluate the receiver equalizer setting.

Nadolny: "The rule of thumb I like to use is found by doing a broad classification of the degrees of equalization in the channel." With relatively simple things - low speed or short trace length - typically there is no equalization. You can accommodate about 7 dB of insertion loss, partition it out, and budget for that. At higher speeds, with a simple pre-emphasis solution for equalization, insertion loss may be 12 dB. At PCIe Gen3 speeds, a more complex solution with continuous time linear equalizer (CTLE) technology can accommodate 20-25 dB of insertion loss.    

Other questions that were asked included:

  • How effective is it to model signal lines with a portion of the power and ground plane?
  • What are the pros and cons of different instrumentation used for signal integrity measurement?
  • What's the accuracy of IBIS simulation and can we really use it to close the design?
  • Is there any way to include power distribution for I/O drivers before IBIS 5.0?
  • Does it matter where in the channel you place the equalizer chip?
  • Will we ever see 100 Gbits/second in copper, and if not, where are the limits?

Want to hear the answers? The webinar is available on demand here.

Richard Goering

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