Can digital verification techniques such as verification planning, coverage metrics, and assertion checking be applied to the analog/mixed-signal world? Yes, according to Pierluigi Daglio, analog verification engineer at STMicroelectronics. In a recorded presentation at the Cadence web site, he shows how his company implemented a metric-driven mixed-signal verification flow, and he discusses its advantages and challenges.
The presentation, titled "A Metric-Driven Verification Approach for Analog/Mixed Signal IP," was one of 30-plus customer and partner presentations at the EDA360 Theater in the Cadence booth at the Design Automation Conference (DAC 2012). Audio recordings and slides from most of the presentations are located here. Daglio also gave an EDA360 Theater presentation on analog intent capture, summarized here.
A metric-driven verification flow is a closed-loop approach (right) that creates an executable verification plan, collects and analyzes coverage metrics, measures progress, and automates verification tasks. It's been highly successful in the digital world. But why apply it to analog/mixed-signal IP verification? "It is almost impossible to have acceptable coverage closure with traditional verification approaches based on mixed-signal co-simulation," Daglio said.
He identified these advantages of metric-driven, mixed-signal simulation:
- You can trace your progress towards coverage closure so that, at any point in time, you know how much of the design has been verified
- The verification environment can be reused, both with a similar product or on various levels of abstraction within a single design
- Simulation speed is faster because you're using event-driven simulation
- Waveform viewing can be replaced with pass/fail alerts from assertions
But there are challenges too. Daglio noted that metric-driven mixed-signal verification requires an additional, initial effort when it comes to defining good metrics for analog verification, creating a detailed verification plan, leveraging real-value models, specifying the hierarchy of transactions, and finding the right sampling rate and sampling windows. Perhaps most importantly, he said, "we need to create a new professional role - a mixed-signal designer who knows all the hard things about analog design, but who understands the advantages of using assertions, language, checkers, and coverage."
Experience at STMicroelectronics
Daglio noted that STMicroelectronics set up a previous mixed-signal verification environment using the Cadence Specman verification environment, a Fast SPICE simulator, and a digital simulation engine. It worked, but it was a multi-vendor environment, giving rise to communications problems between different tools. Long simulation runs were limiting verification closure. So STMicroelectronics decided to put together an all-Cadence verification environment.
This environment is based on the Cadence Incisive platform and uses Specman and the Virtuoso AMS Designer. It uses the Incisive Enterprise Manager for verification planning and Incisive Enterprise Simulator (referred to as NSim in the presentation) for digital simulation. The Specman "e" language environment generates stimulus for the circuit and measures the outputs. "Everything is managed by Specman," Daglio said.
While analog/mixed-signal models can be developed at several levels - including SPICE, Verilog-AMS, and VHDL-AMS - STMicroelectronics places a strong emphasis on Verilog-AMS wreal models, which can model continuous quantities in a pure digital simulator. Thus, wreal models are much faster than co-simulation using a Fast SPICE simulator. In the presentation, Daglio shows how Cadence has expanded the wreal data type beyond the Verilog-AMS language definition, and he also briefly compares wreal to real number modeling in other languages.
Daglio also showed how Specman can represent analog stimulus and trigger transistor-level analog events. He discussed mixed-signal assertions using Property Specification Language (PSL), and talked about how the Universal Verification Methodology (UVM) can be extended to bring metric-driven verification to mixed-signal environments. In future flows, he's looking forward to automatic generation and validation capabilities for analog behavioral models including wreal models.
Making it Work
The presentation closed with an example showing how the metric-driven environment works on a 130nm mixed-signal IP block. (This same example was presented in a "best paper" at CDNLive! EMEA in May. Cadence Community members can read it here). One interesting point is the number of languages and formats used - SPICE netlists, Verilog-AMS modules, UVM monitors, Verilog structural netlists, VHDL-AMS blocks, Specman "e," and PSL and SystemVerilog assertions with wreal datatypes. Everything is controlled from the Cadence irun environment.
The environment "is still a little complex," Daglio said, but there's some real automation that comes from Specman and from PSL assertions. He noted that Incisive Enterprise Manager allows automatic process, temperature and voltage variations, easing multi-corner verification. What's critical now, he said, is for companies to "grow the competency" to deploy metric-driven, mixed-signal environments.
The recorded audio presentation with slides is located here.