For several years, ARM has offered processor optimization utilities (called POPs) that help users of ARM Cortex-A series processors optimize power, performance and area for a given process. This week (Aug. 9) ARM and Cadence took things one step further by announcing a POP that includes scripts that drive Cadence Encounter digital implementation tools, creating an "out of the box" optimized EDA flow for ARM Cortex-A9 designs using the TSMC 40LP process. This collaboration will extend to POPs for the Cortex-A15 and for the TSMC 28HPM process.
It may sound simple in concept, but it took a significant investment and a deep collaboration on the part of ARM and Cadence to couple the ARM POP IP to the Encounter flow. Traditionally, POPs have not been tightly integrated with commercial EDA tools. The Encounter-optimized POP removes a lot of the work that design teams would otherwise have to do themselves. Setting up a flow and writing the scripts that drive it is not trivial, especially if one is trying to optimize results for a given processor and process.
ARM today offers POP solutions for Cortex-A7, Cortex-A9, and Cortex-A15 processors. Cortex-A9 POPs are available for 40nm, 32nm, and 28nm geometries. POPs include three components:
- Artisan physical IP standard cell logic and memory cache instances that are specifically tuned for a given ARM processor and foundry technology.
- A comprehensive benchmarking report that shows the results ARM achieved for the processor implementation across a number of configuration and design targets.
- Implementation knowledge that includes floorplans, scripts, design utilities, and a POP Implementation Guide.
Using these components, ARM promises that design teams can achieve superior power, performance and area when hardening ARM cores, and they'll do so in less time.
Including scripts that drive Encounter tools takes POPs to a new level - adding a fourth component, one might say. Specifically, the Cortex-A9 POP mentioned above supports a Cadence tool flow that includes physical-aware synthesis, floorplanning, placement, routing, extraction, signal-integrity analysis, and design for test (DFT). The integrated Cadence flow includes Encounter RTL Compiler, Encounter Digital Implementation System, Encounter Timing System, and QRC Extraction. The flow also includes clock concurrent optimization (CCOpt), a new technology that combines clock tree synthesis with physical optimization.
Cadence and ARM have been working together for several years to provide optimized tool flows for advanced ARM processors. Last year I wrote about a multi-year technology collaboration that resulted in optimized Cadence design and verification tools for the Cortex-A9 and Cortex-A15. It led to new capabilities in the Encounter flow that improve power and performance with these processors, and help designers avoid timing bottlenecks.
The POP effort "was quite a significant investment in time from our side," said James Davey, marketing director at Cadence. "Scripts needed to be created, and we were acting like a customer would, going from zero all the way through [to hardening the core]." A significant and steady performance improvement occurred during this engineering effort, and now those benefits are available to users.
One point that occurs to me is how commercial EDA tools are "generalized" to handle a broad range of processors and processes. For obvious financial reasons, you don't find tools that are specifically optimized for just one processor and process. But with the ARM-Cadence POP collaboration, you essentially get all the benefits of such a tool. A new level of collaboration has created a new type of offering that will bring a new level of power, performance and area to users of advanced ARM processors.
You can read more about ARM POPs here, and you can read an ARM Community guest blog by Steve Leibson about the collaboration here. The Encounter-optimized ARM POP Cortex-A9 solution is available for licensing from ARM.