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Video: Enabling Next-Generation DRAM with DDR4, LPDDR3, and Wide I/O

Comments(0)Filed under: Industry Insights, TSVs, IP, ChipEstimate, memory, 3DIC, 3D-IC, Greenberg, PHY, memory controller, wide i/o, DDR4, video, LPDDR3, latency, bandwidth, through-silicon vias, wide io, IP Talks, DRAM controller

If you want low-power, high-bandwidth access to off-chip DRAM, you're going to have to do some creative design work. A recent video presentation provides a good overview of some of the challenges, and shows how more intelligent memory controller and PHY IP is needed to support next-generation standards such as DDR4, LPDDR3, and Wide I/O.

The presentation is titled "DDR4, LPDDR3, and Wide I/O -- How Design IP Meets the Needs of Next Generation High Bandwidth, Low Power Memory." It was presented by Marc Greenberg, product marketing director at Cadence, as part of the IP Talks! series at the Design Automation Conference (DAC 2012) at the ChipEstimate.com booth.

Greenberg started the 20-minute talk by noting seemingly conflicting demands. Most applications use off-chip DRAM because the cost per bit is much lower than on-chip memory. However, moving away from the CPU results in longer access times. Meanwhile, applications from smartphones to tablets and PCs are demanding faster bandwidths. Standards such as DDR4, LPDDR3 and Wide I/O will help, but substantial changes are required in the memory controllers and PHYs that provide the connection to off-chip DRAM.

Smart Controllers

In a modern SoC, Greenberg noted, a single DRAM resource is shared across a number of clients. Low latency is needed for critical transactions, and high bandwidth is needed for large transfers. One way the controller can manage all this, and still ensure peak performance, is by reordering transactions so that gaps between them are shorter. Greenberg showed an example in which Cadence memory controller IP provided a 30% performance improvement by reordering transactions.

Other important memory controller capabilities include low-power access modes to control DRAM power, a "broad and rich feature set" to meet the needs of a variety of users, and improved priority reordering to create longer queues without increasing latency. Greenberg noted how Cadence provides both low-power and high-performance PHYs. He also observed that controllers and PHYs aren't enough - there's also a need for verification IP (VIP) and a board-level system integration kit.

Greenberg spoke enthusiastically about the promises of Wide I/O DRAM in conjunction with 3D-ICs with through-silicon vias (TSVs). "By using TSV-based memories, we can improve the number of connections between dies by about 10X," he said. "It's easily possible to have 1,000 to 2,000 connections between any two dies connected together using microbumps. The bandwidth between those dies can be increased by up to 10X, and there's a 6X reduction in capacitance per connection."  He noted, however, that Cadence had to make "quite a few changes" to its DRAM controller to support Wide I/O.

To view the video, click here (ChipEstimate.com log-in may be required) or click on the icon below. For more information about Cadence design IP solutions, click here.

Richard Goering

 

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