If you're currently doing or contemplating IC design at 28nm and below, you no doubt have some questions. One place to get a lot of them answered is an Advanced Node microsite newly launched by Cadence for both digital and custom/analog designers. And one interesting (and new) document you'll find there is titled "20 questions on 20nm."
The new site, accessible to anyone, includes these features:
- Resource Library with whitepapers, datasheets, and technical briefs
- Customer success videos from Ambarella, Global Unichip, GLOBALFOUNDRIES, IBM, Samsung, Silicon Blue, and SMIC
- News and Events including press releases, articles, and archived webinars
- Recent blogs and technical documents
- Links to product information for the Cadence Advanced Node Solution
- Overviews of digital and custom/analog challenges and solutions
While much of the industry discussion around 28nm and below has focused on digital design, the new advanced node site gives equal consideration to custom/analog design. The overview notes that custom/analog designers are concerned about 20nm double patterning, complex layout rules, layout-dependent effects, parasitics that used to be second or third-order effects, and device variation. While the custom design cycle has been manual in the past, more automation is clearly needed, and new methodologies such as quick prototyping and in-design signoff verification will play a vital role.
The "20 questions" cover both digital and custom/analog design as well. And here are the questions:
Q1. What are the key advantages of moving to 20nm, and where are we seeing the most interest?
Q2. Overall, what are the primary design challenges at 20nm?
Q3. Do you really need double-patterning technology (DPT) at 20nm? Can I do without DPT?
Q4. What design challenges come with double patterning?
Q5. What kinds of transistor counts can be expected at 20nm, what should I watch out for, and how can EDA tools help?
Q6. Variability is already a problem at 40nm and 28nm. What is new and different at 20nm?
Q7. What is the new routing layer at 20nm?
Q8. What's needed in a 20nm design tool flow? Will a point tool approach work?
Q9. At which stages of digital implementation does double patterning need to be handled correctly?
Q10. How are electrical characteristics different at 20nm?
Q11. How do 20nm manufacturing requirements affect timing and power signoff?
Q12. If I'm designing sensitive, matched circuits, how do I minimize variation due to double patterning?
Q13. I'm designing layout by hand. How will I manage these 400 new layout rules?
Q14. I'm currently doing Monte Carlo analysis to look at process variability. Can I apply that to LDE?
Q15. Memory continues to grow in significance for SoCs in terms of both area and power consumption. What can be done to reduce leakage power of memories?
Q16: ARM is strong in the mobile market and IP may be optimized for low power. How will your physical IP and POPs work for networking/enterprise applications?
Q17. What are the overall benefits of 20nm process technology?
Q18. Which layer will require double patterning? All of them, or just the metal layers?
Q19. Is pre-coloring necessary?
Q20. Will the coloring done by EDA tools be maintained during manufacturing for mask assignments?
You'll find answers to these and many other questions here.