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Whitepaper: 20nm is More Than Just Double Patterning

Comments(0)Filed under: Industry Insights, lithography, Double Patterning, 20nm, signoff, manufacturability, CTS, ccopt, clock concurrent optimization, clock tree synthesis, 20nm whitepaper, LDE, layout-dependent effects, GigaFlex, variation, PPA optimization, giga scale, giga hertz

Probably the most discussed challenge of the 20nm process node is double patterning, which uses extra masks in order to get lithography equipment to print correctly. That is, indeed, a major change that has impacts throughout the design flow. But as a newly published Cadence whitepaper points out, double patterning only part of a much bigger picture.

The whitepaper is titled "A Call to Action: How 20nm Will Change IC Design." It presents 20nm as a turning point for the electronics industry, one that brings unprecedented gains in power, performance, and area -- but also one that raises serious challenges in manufacturability, "Giga Scale" design complexity, and "Giga Hertz" design optimization. The big picture solution is nothing less than a comprehensive, 20nm-aware custom/analog and digital design flow based on a "prevent, analyze, and optimize" methodology.

The following diagram illustrates the challenges. Silicon manufacturability and variation is probably the most familiar topic, and it includes double patterning, new and complex design rules, and layout-dependent effects (LDE). The whitepaper explores these topics in detail, and shows how double patterning impacts the entire design flow, from cell and library generation in custom IC design environments to placement, routing, extraction, and analysis in digital design environments.

The whitepaper also discusses layout-dependent effects, which are especially tricky because the performance of a device or cell will change according to what is placed near it in the layout. You can't just model a cell in isolation and predict its behavior. As the whitepaper notes, at 20nm up to 30% of device performance can be attributed to the layout context.

Billions of Transistors

Moving beyond manufacturability and variation, we come to the challenge of achieving "Giga Scale" design productivity. At 20nm, a chip may have 8-12 billion transistors, resulting in unprecedented complexity. That, in turn, requires an automated, integrated, end-to-end flow rather than a point tool approach. Automation is especially needed in the analog/custom environment. One capability that will help is a rapid prototyping methodology guided by pre-layout parasitic estimates.

On the digital side, a flexible modeling technology is needed to support multiple levels of abstraction. That's why Cadence developed GigaFlex, a technology that provides just the level of detail that's needed during design phases such as exploration and planning, top and block implementation, hierarchical closure, and ECOs.

Giga Scale design complexity requires a "prevent, analyze and optimize" design and verification flow. This is essentially a correct-by-construction approach in which signoff-quality engines are used during the design flow, instead of saving all the signoff verification for the very end. The flow doesn't replace a final signoff step, but it greatly shortens it. With everything dependent on everything else, the traditional "fix it at signoff" approach will not work at 20nm - not if you want to achieve design closure in a reasonable period of time.

Concurrent PPA Optimization

A final challenge is concurrent PPA (power, performance, area) optimization. This becomes important because of the complexity of 20nm chips as well as the interdependency of all aspects of the design. Further, many 20nm chips will have GHz performance, complex clocking schemes, and multiple power domains. Low-power design will be a mandate in most cases.

Clocking provides one example of the need for concurrent optimization. The traditional approach to clock tree synthesis (CTS) focuses on minimizing clock skew, and performs CTS separately from physical optimization. This results in a timing gap between the ideal clocks used pre-CTS and the propagated clocks that emerge after CTS. Clock concurrent optimization is a new methodology that makes CTS timing window-driven rather than skew-driven, and merges it with physical optimization.

As you can see, 20nm is a lot more than just a switch to double patterning. It really calls for a new way of designing ICs, and changes are needed in both the analog/custom and digital IC design environments. The good news is that all the challenges mentioned here are manageable given 20nm-aware tools, a "prevent, analyze and optimize" methodology, and deep collaboration throughout the semiconductor design and manufacturing ecosystem. For more information, you can read the whitepaper here.

Richard Goering



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