Home > Community > Blogs > Industry Insights > si2 dac panel what standards are needed for 3d ics
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Si2 DAC Panel: What Standards are Needed for 3D-ICs?

Comments(0)Filed under: Industry Insights, DAC, TSVs, Qualcomm, Si2, DFT, Panel, Power, Atrenta, collaboration, signal integrity, Silicon Integration Initiative, 3D IC, 3D-IC, pathfinding, Cadence, thermal, Altera, Sarkar, ecosystem, Petranovic, PDN, Design Automation Conference, design for test, 3D-ICs, Bansal, chip package interface, 3D: Radojcic, Samoylov, 3D IC standards, Open3D TAB, Chandrasekar, Varadarajan, 3D-IC standards, Invarian

3D-ICs with through-silicon vias (TSVs) are not yet in volume production, but work has already begun on design standards - and more work is needed soon. An excellent update on work in progress, and a discussion of what's needed, was provided at a Silicon Integration Initiative (Si2) panel discussion at an "Si2 Round-up" co-located with the recent Design Automation Conference (DAC 2012).

The panel began with an update on the Si2 Open3D TAB (Technical Advisory Board) given by its chairman, Riko Radojcic, director of engineering at Qualcomm's CDMA Technology Group. Other panelists included the following (in order of their opening presentations):

  • Karthik Chandrasekar, member of technical staff, Altera
  • Aveek Sarkar, vice president product marketing, Apache Design (now part of Ansys)
  • Samta Bansal, product marketing manager, Cadence
  • Dusan Petranovic, technical marketing engineer, Mentor Graphics
  • Alex Samoylov, vice president of engineering, Invarian
  • Ravi Varadarajan, fellow, Atrenta

Currently 18 companies are members of the Open3D TAB, including all the companies listed above.

A recurring theme throughout this discussion was the diverse ecosystem that's needed to produce 3D-ICs. It includes many different kinds of providers, as shown in the diagram to the right. It will include tools from different EDA vendors, and in many cases, dies from different sources. There are thus a number of "handoffs" between different providers and tools, and there must be some kind of common language so everyone can understand what is being handed off.

Open3D TAB - Lubricating the Supply Chain

Standards, said Radojcic, are "a lubricant to the supply chain." He noted that Qualcomm and other companies are relying on a distributed supply chain, and that standards are vital for facilitating the handoff between one provider and another. Radojcic pointed to two different kinds of standards that are being developed in parallel. One is process standards for such concerns as wafer thinning and inspections; these are under development by SEMI and Sematech. Another is the design standards under development by Si2, IEEE, JEDEC, and Global Semiconductor Alliance (GSA).

"For me the intent of standards is to facilitate communication between memory die and stack design, and custom die and stack design and the other way around. Let's figure out what types of design information need to be sloshed around and then let's settle on some kind of format that can slosh this design information around," Radojcic said.

 Radojcic identified seven types of information that need to be "sloshed around:"

  • Power Distribution - Ensure that each die in the stack has access to the required power supply
  • Thermal Management - Ensure that the stack is not adversely affected by thermal hot spots or gradients
  • Pathfinding - Facilitate communication of overall design intent and constraints
  • Physical Verification - Facilitate stack-level physical DRC verification
  • Signal Integrity - Facilitate stack-level electrical modeling
  • Stress Management - Ensure dies are not adversely affected by stack-level stress hot spots or gradients
  • Design For Test - Faciliate post-stacking testability and observability

The Open3D TAB has launched dedicated working groups in the first three areas above - Power Distribution Network (PDN), Thermal Management, and Pathfinding - and will take up the other topics later. Radojcic said, "we have three working groups in flight, and we are looking for them to hand off a standard soon-ish. And we are hoping to have the first batch of 3D design exchange formats this year."

So What Else is Needed?

Chandrasekar (Altera) provided a list of "near term" (1-2 years) and "long term" (2+ years) needs for standards. Near term needs include a set of "good practices" for 3D integration, interoperability with existing tool sets, interfaces between multiple dies, and a 3D process design kit (PDK). Long term needs include material and structural attributes for pathfinding, a data exchange format for interoperability between IC design tools, and a data exchange format for chip-package co-design.

Sarkar (Apache) provided a closer look at the activities of the Open3D PDN working group. Its charter, he said, is to come up with a "simplified equivalent circuit to model load and parasitic to enable stacked die PDN design and verification." Working group members are working towards model standardization, targeting areas including model generation, interfaces, validation, design exploration, and implementation.

"What we have achieved so far," Sarkar said, "is that we have defined what the power model should contain, what benefits the model should provide, and what we should not give out in details, so you do not divulge too much of your IP. We are also making good progress on defining an interface." The working group has version 1.4 of a Chip Package Interface Protocol (CPIP) spec.

Bansal (Cadence) noted that a very complex 3D-IC ecosystem requires collaboration between different parties - EDA and IP providers, foundries, outsourced assembly and test (OSAT), packaging houses, and more. Just like in a big company where there are multiple "views," there must be some standardized processes for communication. Standards are also needed on the manufacturing side, she noted: "How are we going to standardize in test? What are the assembly procedures, wafer handling mechanisms, and materials that will be used?" The business model is also a big question - who is going to be responsible for reliability and yield?

Petranovic (Mentor) talked about the need for standards for electrical modeling for timing and signal-integrity analysis. One big question is TSVs - are they vias or devices? What kind of coupling between TSVs needs to be taken into account? "There is still uncertainty about what should be modeled and what is really important to be modeled," he said.

Samoylov (Invarian) focused on 3D thermal standards. With 3D-ICs, he noted, we will go from a single slice of silicon to a real 3D structure with thermal properties, and thermal effects that are "pretty much unpredictable." Microbump arrays and TSVs will have a significant impact on thermal characteristics. Dies from different vendors will be assembled into 3D stacks, and thermal analysis cannot be done by a single vendor. Samoylov said there is "very strong demand" for a common format that will express thermal characteristics.

Finally, Varadarajan (Atrenta) gave an example of why the Pathfinding working group (which he's on) has an important task. "A single 3D design decision, such as changing one die from face up to face down, completely changes the physical model," he said. "To characterize that effectively you need standards, because it's going to change your parasitics and your timing, and change all the decisions you need to make."

Presentation slides from these speakers (except Varadarajan, who had no slides) are available here.

Richard Goering

 

 

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.