will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Blogs > Industry Insights > dac 2012 panel tackles tough questions about 2 5d ics and 3d ics
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DAC 2012 Panelists Tackle Tough Questions About 2.5D-ICs and 3D-ICs

Comments(1)Filed under: EDA, Industry Insights, FPGA, DAC, DFM, Intel, IBM, Simulation, Xilinx, Madden, stacked die, 3D, TSV, analysis, test, TSMC, yield, 3D-IC, Cadence, extraction, packaging, 2.5D, silicon interposer, 3D ecosystem, CoWoS, Iyer, Lee, known good die, Borkar, DAC panel, assembly, Incorvaia, 3D panel, 2.5D-IC

In a sometimes contentious panel session at the Design Automation Conference (DAC 2012) June 7, experts discussed and debated key technology and business questions around 2.5D-ICs and 3D-ICs. One overall takeaway is that 2.5D technology is very close to volume production, but true 3D stacking raises some issues that still need to be resolved.

The panel was titled, "Is 3-D Ready for the Next Level?" It was moderated by Sachin Sapatnekar, professor at the University of Minnesota, who provided a number of probing questions. Panelists were as follows, in order of their opening statements:

  • Shekhar Borkar, director of extreme scale technology, Intel
  • A.J. Incorvaia, vice president of R&D for the Cadence PCB and IC Packaging group
  • Subramanian Iyer, fellow at IBM Systems and Technology Group
  • Suk Lee, director of design infrastructure marketing, TSMC
  • Liam Madden, corporate vice president of FPGA development, Xilinx

Since the discussion covered both 2.5D-IC and 3D-IC technologies, here's some quick background. In general, 2.5D refers to multiple silicon dies placed side-by-side on a silicon interposer substrate. A "true" 3D-IC stack involves two or more dies stacked on top of each other, with interconnect provided by through-silicon vias (TSVs). Often both 2.5D silicon interposer and 3D stacking technologies are lumped together under the "3D" label.

Here are some of the questions - and answers - that came up during the hour-and-a-half discussion.

What is 3D technology good for?

Borkar (Intel): "3D is not good for the integration of logic to reduce interconnect delay. It is good for the integration of heterogeneous technologies - analog, digital, nonvolatile memory, opto-electronics, and so on. It is also good for reducing system-level interconnect energy."

What's needed from an EDA perspective?

Incorvaia (Cadence): There are many varieties of 3D-IC, and all pose significant challenges to EDA tools. "We have to make sure we can handle not just interposers and 2.5D, but also full 3D with logic plus memory. We have to be able to do extraction and analysis. We've made significant progress with design tools, but there's quite a bit of work to be done in the system partitioning space. One thing we need to make sure of is that we not only support design from a custom or digital perspective, but that we're also able to bring these together and take the package into consideration."

Madden (Xilinx): "We really need some better simulation models. We've done test chips for 6 years. The time we got a real breakthrough is when we got a thermal-mechanical simulation capability."

Borkar: "The capabilities that don't exist are hot buttons such as system-level. I don't know how to do my partitioning."

Madden: "I don't think there's an added set of system level issues. Most issues we struggle with are right at the silicon level. What I worry about most is taping out something that comes back with opens and shorts."

When will volume production start? And for what applications?

Lee (TSMC): TSMC has developed the CoWoS [chip on wafer on substrate] 2.5D process, which mounts heterogeneous dies on a silicon interposer. TSMC will roll out a reference design flow in October and go into production in 2013. (Note: For more information on CoWoS and the Cadence participation in its development, see my recent blog post).

Madden: Xilinx last year announced two (2.5D) products that are shipping today. The technology offers about 2X the density of a monolithic FPGA and about 3X the bandwidth.

Borkar: 3D-IC adoption will start in the commodity market, where form factor is crucial.

Iyer (IBM): "I disagree. Like everything else these things happen first at the high end. I believe in trickle-down theory, the Reaganomics of the silicon business. The cost of these technologies will be rather high."

How difficult is 2.5D technology?

Madden: "It really isn't that hard - you just have to do it. Beware of the FUD [fear, uncertainty and doubt]. I would say, to anyone interested in doing 3D work, just go ahead and do it - you'll find it's just good old fashioned engineering."

How does 3D compare to monolithic integration?

Iyer: "We've done a lot of analysis and if there is a way to integrate monolithically, it is always a superior solution to integrate monolithically."

Madden: "Would you take that all the way to an 800mm2 die?"

Iyer: "You could."

Madden: "At what cost?"

Iyer: "There's a cost."

Iyer: (later) "Let's flip this problem in a different way. I now let you work with multiple chips - 8,9,10 dies - and the level of integration you can get is humungous. But how are you going to package that? What you've done is transferred the problem to another guy, the packaging guy."

How important is it to have 3D die stacking vs. the 2.5D approach?

Madden: "The idea that you need true 3D stacking is a problem in the industry - it's the great being the enemy of the good. Yeah, it's great to say you're going to stack 3 dies on top of each other, but that brings huge thermal and floorplanning issues. I think you can do amazing things with the 2.5D approach."

Lee: "We certainly agree that you can get a lot of the benefits of full 3D stacking through 2.5D. A large part of that is reducing the system interconnects. For the first time in a long time, you do get a free lunch."

Incorvaia: "We have to walk before we can run. 2.5D interposer is a great way to start the journey."

What will 3D systems look like in 2015?

Madden: "By 2015 we'll be looking back and wondering, why were we so worried about this?"

Borkar: "I'm not that optimistic. I'll tell you why. Things move slowly. There are still a lot of issues that need to be addressed - testing, known good die, modeling issues."

Who will manufacture 3D-ICs? And who takes responsibility if things go wrong?

Lee: TSMC is offering an "integrated manufacturing capability" with CoWoS. "We believe the necessary evolution is that the silicon integration happens at the semiconductor manufacturer."

Madden: "I'm always concerned about something contained within one entity. I'd like to see competition across multiple entities."

Lee: "In this initial offering, we're taking ownership of that [responsibility] problem."

Madden: "This [responsibility] is the key question. The guy who's first building these things has to take responsibility. On the other hand I don't think this solves the long-term business issue."

What's the most under-represented issue in 3D?

Borkar: "The top under-represented issue is testing. You're not testing a chip, you're testing a system.

Incorvaia: "I would say testing and debug - when you find a problem, how do you find where it is."

Madden: "There's not a lot of work in the DFM [design for manufacturability] area. There's a big body of work to be done."

Iyer: The assembly process - "there isn't a similar technique today. We don't know how we're going to do it." Two other problems are wafer-to-wafer alignment, and getting good yield from a stack of dies.

Sapatnekar concluded the panel by asking if 3D is indeed ready for the "next level." Iyer suggested that we should finish the current level first. Incorvaia cited "good progress," and Lee and Madden both simply said, "we're doing it." Borkar wrapped things up neatly by noting that 3D "has a lot of challenges, but is very promising if you use it for the right thing. For the wrong thing, it's not going to work."

Richard Goering

Industry Insights blog posts about DAC 2012

ARM CTO at DAC 2012: The Truth About Semiconductor Scaling

DAC 2012 Panel - Can One System Model Serve Everybody?

DAC 2012: EDA Industry Celebrates 10 Years of OpenAccess

TSMC-Cadence Collaboration Helps Clarify 3D-IC Ecosystem

Gary Smith at DAC 2012: Multi-Platform Design and the $40M System on Chip

DAC 2012 IBM Keynote: Multi-Core Performance Growth Slowing, New Approaches Needed

DAC 2012: How Unified Coverage Interoperability Standard (UCIS) Will Ease IC Verification

DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm




By Zvi Or-Bach on June 15, 2012
We agree with IBM: "We've done a lot of analysis and if there is a way to integrate monolithically, it is always a superior solution to integrate monolithically." . And the good news, MonolithIC 3D breakthrough is finally makes it practical utilizing existing fab and well practice semiconductor processes. Please visit to learn more.

Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.