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DAC 2012 Panelists: How to Succeed at 28nm, 20nm and 14nm

Comments(0)Filed under: Industry Insights, ARM, DAC, low power, SoC, IBM, HKMG, 3D, TSV, GlobalFoundries, collaboration, 28nm, fabless, Patel, yield, 20nm, Patton, 3D IC, 3D-IC, Cadence, Samsung, design rules, foundry, Chian, physical IP, Hsu, FinFET, 14nm, DAC 2012, Cadence breakfast, planar devices, IDM, 20nm tools, Choi, 2(x)nm, DAC breakfast

What will it take to achieve silicon success at 28nm and below? That was the question put to a panel of experts at a Cadence-sponsored breakfast at the Design Automation Conference (DAC 2012) June 6, where speakers from IBM, Cadence, ARM, Samsung, and GLOBALFOUNDRIES shed new light on business and technology challenges and solutions.

The panel was titled "The Path to Yielding at 2(x)nm and Beyond," and was moderated by Steve Leibson (leftmost in photo below), marketing director at Cadence and author of the EDA360 Insider blog. It would be hard to find a more qualified panel. Panelists were as follows, listed as shown from left to right:

  • Gary Patton, vice president of IBM Semiconductor Research and Development Center
  • Chi-Ping Hsu, senior vice president of R&D, Silicon Realization Group, Cadence
  • Dipesh Patel, deputy general manager, ARM Physical IP Division
  • KM Choi, senior vice president of the Semiconductor Business at Samsung Electronics
  • Mojy Chian, senior vice president, Design Enablement, GLOBALFOUNDRIES


20nm panelists at Cadence breakfast, DAC 2012

"Success at 2(x)nm nodes is a difficult topic, but here are some of the most experienced people on the planet who can advise you where the potholes are going to be, because they've already stumbled into a few of those potholes themselves," Leibson said.

Gary Patton - End of the Planar Device Era

"Technology scaling is not over," said Patton, who has responsibility for IBM's semiconductor roadmap, operations, and technology development alliances. "But it's going to be a lot harder to move the technology forward and achieve the performance, power, and density requirements that will make the technology inviting to customers." Noting that innovations such as high-k metal gates (HKMG) may take 10 years of research, he asserted that the time for new technology development is now. He also stressed the importance of collaboration and the need to "operate more as a virtual IDM with our customers and our EDA partners."

Patton noted that the semiconductor industry runs into a wall about every ten years. This happened with bipolar technology in the 1980s, which proved to be too power-hungry. Planar CMOS took over around 1990 and scaling worked well for a while. Then, around 2000, gate oxide got so small it couldn't scale any more. Techniques like strain engineering and HKMG have kept things going - but now, Patton said, we are coming to "the end of the planar device era."

What's next is the "3D era," in two different ways. One direction includes 3D devices, specifically FinFETS or tri-gate transistors. The other involves 3D die stacking with 3D-ICs. But it doesn't stop here. "We believe 3D FinFETS and 3D integration will take us into the early 2020s, but at some point we will reach an atomic dimension limit, in which case we'll need some novel devices," Patton said. "This is going on in research today with things like silicon nanowires, carbon nanotubes, and the integration of photonics onto the wafer."

Chi-Ping Hsu - Investing in Advanced Nodes

Hsu noted a dilemma. Advanced process nodes generate hundreds of design rules, but with all these rules, can people still generate good designs? "At the end of the day, if we make spacing larger, if we make voltage higher, we solve some problems, but then we don't get the density, frequency and power advantages of process developments. So the worry is always whether the designer can design optimally enough."

A side effect of all these rules is an explosion in the physical design team. Hsu read a quote from an nVidia manager who talked about increasing the size of the physical design team by 30X for 28nm. Another quote from a top semiconductor company stated that it takes 5X the number of people to do 20nm design compared to 65nm design, with 4-5 layout people for each designer at 20nm, compared to 3 designers for every layout person at 65nm.

While people talk about process, design, and fab costs at 20nm, they don't talk about EDA costs, Hsu noted. "The EDA industry as a whole, by the time we have 20nm in production, will probably spend a billion dollars in pure R&D development," he said. He noted that Cadence has 600-700 people working on 20nm tool development, including digital, custom/analog, signoff, design for manufacturability (DFM), and IP. It's a heavy development cost, but it has produced a solution that addresses all these areas.

Dipesh Patel - Challenges of Physical IP at 2(x)nm

Nobody is going to design 20nm SoCs until the physical IP is available, and Patel talked of the challenges ARM has encountered in producing it. One challenge is that the rules are so complex it's been necessary to come up with a "simple set of patterns" that designers are allowed to use, rather than trying to tell them all the things they can't do. Patton made the same point as he talked about the move from "restrictive" design rules (what you can't do) to "prescriptive" design rules (what you can do).

Patel noted that voltage hasn't scaled a lot in recent years, so ARM is having to do some circuit design innovation to reduce power consumption. This involves, for instance, complex assist schemes in the memory compiler. Another challenge is double patterning, which forces layout to be color-aware. "We can't just hire 5X the number of mask designers, because they don't exist," he said. "So, we have looked at how we can apply automation to that problem."

Yet another problem is that signoff complexity is going up, with 30 to 40 corners needed for SoC signoff. This translates into new demands on IP development, including multiple cycles of silicon validation.

KM Choi - Promising and Demanding Technologies

Choi noted four technologies that are "preparing a path to the future." These are double patterning, FinFETs, low power, and through-silicon vias (TSVs). But they don't come for free, and they all have their challenges. For instance, double patterning requires a decomposition method and a router that can support double patterning rules. FinFETs require SPICE modeling. TSVs raise thermal issues.

"We are making good progress in developing these kinds of things," Choi said. However, he noted that "we cannot complete this kind of work by ourselves. We need diverse collaboration."

Mojy Chian - "IDM Like" Collaboration is Needed

"The foundry business is thriving and will expand, but the engagement model between fabless companies and the foundries is changing," Chian said.  What's happening, he noted, is that design and manufacturing are no longer distinct development activities.

"The model we are moving towards is a virtual integration of design and manufacturing," Chian said. "It is an IDM-like model, where you have the benefits of a very close collaboration between design and manufacturing without having the economic issues of owning an $8 billion fab. This is a model that will become a must at 20nm and beyond."

What's Driving All This? A Teenager!

Speaking from the audience, EDA blogger Gabe Moretti asked what kind of volume, and what kind of price point, will justify the kind of investment that's needed for advanced process nodes. Chian responded that GLOBALFOUNDRIES is increasingly working with customers who have large market shares and revenues and are "very aggressive in adopting leading edge technologies."

What drives them to do that? "My 16-year old son," Chian responded. "He is the biggest consumer of electronics in my house and he is also the biggest user of bandwidth in my house. So the end market is going to be there and it is going to drive to lower power."

"We have a huge opportunity ahead of us," Chian concluded. I think his son would agree.

Richard Goering

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