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Gary Smith at DAC 2012: Multi-Platform Design and the $40M System on Chip

Comments(1)Filed under: Industry Insights, ARM, ESL, SoC, Intel, IP, IP Reuse, Tegra, Gary Smith, OMAP, 2011, DAC 2011, EDA revenues, system level design, platforms, EDA forecast, DAC 2012, Snapdragon, Gary Smith EDA, silicon virtual prototoype, platform based design, multi-platform design

Veteran EDA analyst Gary Smith started his annual Design Automation Conference (DAC 2012) presentation with three simple words: "I was wrong." Wrong, that is, about last year's observation that it takes $75 million or more to design the average high-end mobile semiconductor design. Smith discovered a new way to design that cuts that cost considerably, and it's called "multi-platform design."

In the same presentation, given Sunday evening June 3, Smith noted that the EDA industry grew by 12% in 2011 and said that electronic system level (ESL) design grew by an outstanding 75%. So perhaps last year was the long-awaited "year of ESL." This year, Smith said, may be the year of the silicon virtual prototype.

Smith doesn't mind being wrong in 2011 - in fact, he said that was the "most successful DAC ever," because three companies called him right afterwards to tell him about their work with multi-platform based design. This approach accomplishes three things - it uses already developed software, it reuses IP including verification suites, and it significantly reduces the number of blocks. This reduces the cost of system on chip (SoC) design to $39.8 million, considerably below the $50 million target that large IDMs would like to see, and getting close to the $25 million that is the limit for many venture capitalists.

Because of multi-platform design, Smith said, "we're seeing a takeoff in the industry both in semiconductors and EDA."

Defining Multi-Platform Design

Sharon Tan, analyst at Gary Smith EDA, then came on stage to provide some more detail. She said that multi-platform design is a methodology based on the integration of already existing platforms, with the addition of new applications platforms to add a competitive advantage. As a result of the methodology, it may only be necessary to design 10-15% of an SoC, resulting in costs lowered by 30-40%.

Tan identified a hierarchy of three types of platforms. Starting from the bottom, they are as follows:

  • Functional Platforms represent the core of a design, are not geared to any particular industry or market, and often come from third parties. They may include a processor, memory, and bus structure. Processor subsystems from ARM or Intel are examples.
  • Foundation Platforms are also typically from third parties, but they bring in some market differentiation. Most focus on the mobile and consumer markets. They leave some room for differentiation. Examples include Texas Instruments OMAP, Qualcomm Snapdragon, and NVidia Tegra 3.
  • Application Platforms are usually proprietary, and this is where the product differentiation comes from. They have short product lifetimes and may later blend into foundation or functional platforms.

So what does all this mean for EDA? Smith said that the set of tools required for library development will be different from tools that do systems development. The new methodology, he said, "is going to blow open the market. This is where you see the explosion in system level design. It's pretty exciting stuff."

A Rosy Outlook

As in previous years at DAC, Smith offered an updated EDA forecast. In 2011, he said, EDA industry revenues grew by 12% to $4.98 billion. Gary Smith EDA expects 12.9% growth this year to $5.63 billion in 2012.

Most impressive, however, is Smith's claim that 2010 was the "knee of the curve" for ESL adoption. He said that ESL grew 75% in 2011 to $460 million. Much of that is driven by verification. The number includes virtual prototypes, transaction-based emulation and acceleration, and hardware/software co-design.

Smith also said that 2012 may be the year of the "silicon virtual prototype," which he distinguishes from the more familiar "software virtual prototype." The silicon virtual prototype has two phases. In the first phase, the design starts, hardware accelerators are added, and transaction-level models are developed. In the second phase, existing RTL blocks are inserted, SystemC blocks are synthesized, and a golden netlist is the output.

It's too early to say whether Smith will be right or wrong in 2012. But he raised some thought-provoking points on the eve of DAC 2012.

Richard Goering

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By Consultant on June 19, 2012
Smith is absolutely right.  Multi platform design will greatly reduce the cost. Due to growing functional complexity, ESL based Virtual prototype models aiding for perforamnce analysis for early detection & correction of system level issues will be in demand.

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