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Semico Conference: “System Driven” Semiconductor IP Leads to IP Subsystems

Comments(0)Filed under: Industry Insights, 3D ICs, SoC, Semico, IP, Kapoor, IP quality, system on chip, PCI Express, semiconductor IP, PCIe, silicon IP, 3D-ICs, NVM Express, NVMe, IP subsystems, system-driven IP, Impact, Feldhan, IP ecosystem, design factory

A "new breed" of semiconductor intellectual property (IP) is required for the next stage of evolution in the IP ecosystem, according to a keynote speech by Vishal Kapoor (right) of Cadence at the Semico Impact Conference May 16, 2012. This new type of IP will be "system driven," and it will include IP subsystems, which was also the topic of a panel discussion that followed the keynote.

Kapoor is vice president of marketing for SoC Realization at Cadence. The Impact Conference, held in San Jose, California, was a day-long event about the IP ecosystem that included five keynotes and two panels. In addition to IP subsystems, topics included IP ecosystem collaboration, realizing more value for IP, the roles of big and small IP providers, IP quality, and IP for 3D-ICs.

Jim Feldhan, Semico president, opened the conference with some forecast data. He said Semico is expecting that the semiconductor industry will grow 9% in 2012, compared with 1.3% in 2011. However, the system-on-chip (SoC) market grew 12% in 2011. Semiconductor IP will grow from around $3 billion in 2012 to $6 billion in 2016. IP subsystems will grow from around $300 million in 2012 to $1.2 billion in 2016, a 44% compound annual growth rate.

IP subsystems, Feldhan said, are "a new part of the IP market and we think the race has started to see who's going to be leading this market. It will be spread out over a variety of applications." However, he declined to define "subsystem," noting that the panel was preparing to tackle that task.

The System-Driven Approach

Kapoor identified several phases of the relatively young semiconductor IP market. The early industry, he said, was "much like a bazaar" where the only questions were, do you have the IP and how much does it cost? That worked with one or two pieces of IP, but as SoCs went beyond that, the integration costs were too high. That led to the "megastore" concept where one source would attempt to provide all the IP a design team needs. That, also, turned out to be insufficient as the number of IP blocks in a complex SoC approached 100.

One problem is quality. "Quality is not just does it work as advertised," Kapoor said. "Quality takes the perspective, does it work in my system? Can I configure it in my system? Is this controller going to work the same way in my system as in someone else's system?"

"The thesis we have," he said, "is that the industry needs a new breed of IP that is built by design from the beginning to take the system context in view. It has to be system driven from the top down, not IP driven." And, Kapoor said, it needs to come from a process-aware "design factory" that is designed to build system-aware IP.

So what makes IP system-aware? One criterion is that "when you give me a set of things related to each other, give me those pieces in a form that is tied together." Another is that the IP is designed from the start for easy integration into the end system. And these criteria lead to the concept of IP subsystems.

What is a subsystem? "If you integrate related pieces of functionality and provide an integrated block at a greater level of abstraction than before, and it works in the end system, now you are starting to provide some of the value of the subsystem," Kapoor said. As it happens, Cadence announced an NVM Express IP subsystem the day before the Semico conference, and I blogged about it here. As shown in the lower left of the following diagram, the subsystem includes an NVM Express controller, PCI Express controller, PCI Express PHY, and configurable firmware API - and the configurability is a key part of what makes it "system ready."

 

"Today we need a breed of IP that you can't do with a bazaar and you can't even do with a megastore. You've got to do it with a design factory because it's better by design," Kapoor said.

So What Is an IP Subsystem?

Trying to define the word "subsystem" can be like the story of the three blind men and the elephant, but the panelists who followed Kapoor gave it a try. Steve Roddy, vice president of marketing at Tensilica, noted that the word "subsystem" implies multiple programmable blocks. But the definition is "in the eye of the beholder." Roddy noted that he once worked on a 5-chip MPEG encoder that, today, is a single block - nobody would call it a "subsystem."

Mike Gianfagna, vice president of marketing at Atrenta, said that "a subsystem is a collection of blocks that performs some kind of function using some kind of domain expertise you don't have." It can include hardware and software, and typically there is some level of configurability.

Here are a few other points that panelists made about IP subsystems:

  • You can't just slap random components together and call it a subsystem - the components have to be related functions. No "cats and dogs," as Roddy put it.
  • It's best to avoid two similar kinds of subsystems from two different vendors on the same chip.
  • IP subsystems need early analysis - an error could bring down the whole subsystem.
  • IP subsystem verification will be challenging - you can't test all possible configurations.
  • Subsystems may raise the barrier to entry and reduce the number of IP providers - which may not be a bad thing, given the number out there now.

A final comment was that 3D-ICs shed a whole new light on what is meant by an "IP subsystem," because now a subsystem could be an entire silicon die in a stack. But that's another discussion for another time and for future blog posts.

Richard Goering

 

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