No 20nm IC design "solution" is complete without a custom/analog flow that can develop standard cells and analog/mixed-signal IP blocks. That custom/analog flow requires some changes to keep up with 20nm challenges such as double patterning and layout-dependent effects (LDE). A good overview of what is required, and what capabilities are now becoming available, comes from a newly archived May 3 webinar that included speakers from Cadence and IBM.
The webinar was the third of a 3-part Cadence 20nm webinar series that also included a 20nm overview and a webinar that focused on 20nm digital design. Speakers in the custom/analog webinar were John Stabenow, group director of product management at Cadence; Jeremiah Cessna, director of product management at Cadence; and Keith Barkley, senior software engineer at IBM.
Stabenow launched the webinar with some good news and bad news. The good news is that 20nm can provide a 20% performance improvement, 30% power savings, and up to 50% area reduction compared to 28nm. The bad news is that 28nm is "painfully expensive" in terms of process and infrastructure, and that it provides challenges including LDE, double patterning, new interconnect layers, "difficult" design rules that are too numerous to memorize, and perhaps new types of transistors. And given that many early 20nm adopters will be in the mobile market, time-to-market isn't about to ease up just because of these challenges.
What IBM Needs at 20nm
Barkley gave a good overview of the custom design capabilities that IBM needs at 20nm. He works in the Systems and Technology Group at IBM, which is responsible for high-performance processors such as the Z Series and P Series (the latter being the brains inside the "Watson" computer that starred on "Jeopardy" in 2011). Barkley noted that his group uses Cadence Virtuoso tools for its custom design work.
Barkley said that IBM's requirements for a "next generation" design environment include the following:
- An automated, "correct by construction" environment that can handle complex design rules and constraints
- The capability to create layouts quickly and feed layout information back into the simulator
- Color-aware design tools (colorization indicates which layout features go on which mask for double patterning)
- Flexibility built in to handle "unknowns"
- A complete, integrated solution that can support a complex, hierarchical design flow and methodology
"We have been working with Cadence for quite some time on the development of our next generation Virtuoso design environment that will address our multi-patterning design requirements," Barkley said. Attributes of this environment include design-rule driven color-aware editing, local interconnect support, design rule and color checking, layout decomposition and color balancing, and the integration of the Physical Verification System within the Virtuoso design environment.
Should designers do the colorization, or should this be done during the manufacturing stage? It's a controversial issue, but IBM strongly believes it's a designer responsibility. Barkley cited a number of reasons. Color is not a local problem, he said; it needs to be managed in the design hierarchy as the design proceeds. Designers shouldn't have to recompute colors every time they change the design. And designer colorization is needed to enable a design-rule driven (DRD) methodology for custom design.
A New Custom Methodology
Stabenow then gave a more detailed view of the new custom methodology that Cadence is providing for advanced nodes including 20nm. "What's really different is that throwing stuff over the wall is not going to work any more," he said. "A circuit designer cannot do his work in isolation from the layout design, and the layout designer cannot do his work in isolation from the impact of the layout on circuit performance."
A next-generation custom flow is shown below. The boxes on the left-hand side reflect circuit designer tasks, while the boxes on the right concern layout design. So, there's still a distinction between circuit and layout designers, but they will work in a more collaborative fashion. Circuit designers will use constraint-driven design, an advanced simulation environment, and a pre-layout and post-layout parasitic estimation. The circuit designer also has to understand how sensitive a component might be to LDE, and simulate for that sensitivity before the layout has started.
On the layout side, Modgens can be used by either circuit designers or layout designers to quickly generate layouts for regular structures. It might not be the most area-efficient or aesthetic layout, but it's enough to run a device parameter extraction and provide some meaningful parasitic data for simulation tools. This enables a capability called "rapid analog prototyping." Another important capability on the layout side is in-design signoff, which shortens final signoff runs by employing signoff-quality engines during the design flow.
Stabenow provided some in-depth explanation of LDE and its causes, including well proximity effect, length of diffusion, and poly spacing effect. "As much as 20 to 30 percent of the circuit's performance can be attributed to the effect of the surrounding [layout] environment," he said. One solution is rapid analog prototyping using Modgens.
Stabenow also discussed double patterning, and showed how difficult it is to fix one double patterning violation without causing others. Virtuoso makes double patterning easier by offering hints about double patterning violations as users draw, and by providing real-time, signoff-quality checking that can detect an error before it gets buried too deeply in the design.
Finally, Stabenow talked about the integration of the Physical Verification System into Virtuoso, where it can provide interactive editing checks while designers are creating geometry, as well as post-edit signoff quality checking.
The webinar concluded with some short video demos narrated by Jeremiah Cessna. You can access the one-hour archived webinar free of charge here.
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