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Cadence, Samsung Detail 20nm RTL-to-GDSII Methodology

Comments(0)Filed under: Industry Insights, ARM, encounter timing system, Encounter, EDI, digital implementation, Double Patterning, webinar, 20nm, Cadence, Samsung, extraction, QRC, routing, digital, 20 nm, physical IP, Tan, placement, Encounter Power System, EPS, Lin, LELE, mask misalignment, Physical Verification System, DPT, FlexColor, Cortex-A0, dipole lithography, PVS, mask shift, SPEF, ETS

In a recently archived May 2 webinar, speakers from Cadence and Samsung described a 20nm digital design methodology that can manage challenges such as double patterning, variability, and complexity. The webinar discussed EDA tools, physical IP, and 20nm process technologies, and it highlighted a "proof point" in the form of a 20nm test chip developed in 2011 by Cadence and Samsung.

The webinar was presented by Wei Lii Tan, senior product manager at Cadence, and Dr. Kuang-Kuo Lin, director of foundry design enablement at Samsung. It was the second of a 3-part Cadence 20nm webinar series that also included a 20nm overview by Cadence and ARM as well as a webinar on custom/analog 20nm design by Cadence and IBM.

Few if any products on store shelves right now use 20nm ICs, Tan acknowledged, but he said that within the next few years we will start seeing "much faster, more integrated, and smaller" products resulting from 20nm technology. "We will be able to create more differentiated products in the near future," he said. "Going to a new process node allows us to shift the entire timing/power tradeoff curve down to a more advantageous region."

Challenges and Solutions

Tan identified a number of 20nm technology challenges, including:

  • Silicon Manufacturability. More than 400 new advanced layout rules, as well as additional double patterning rules, must be considered in routing to ensure printability.
  • Timing Variability. Wires are getting thinner and longer, resulting in increased coupling and signal integrity issues. There are more parasitics in device modeling, and layout dependent effects are becoming more prominent.
  • Design Size and Complexity. 20nm designs will be larger and more complex, requiring substantial IP reuse and calling for power management across silicon, package and board.

The rest of the webinar focused on solutions, starting with Samsung 20nm process families and physical IP. Lin showed that Samsung has two 20nm families, the 20LPE and 20LPM. Both use a core Vdd of 0.9V, along with a 90nm logic critical poly pitch. SRAM structures are slightly different. But the main difference is that 20LPE uses a metal pitch of 80nm and uses double dipole lithography, whereas the 20LPM uses a 64nm pitch and employs "true" double patterning using the litho etch, litho etch (LELE) technique.

Samsung 20nm physical IP includes multi-channel and multi-Vt logic libraries, 8 memory compilers, processor optimization packages for the ARM Cortex-A7 and Cortex-A15, and interface IP for DDR3 and GPIO.

An RTL-to-GDSII Design Flow

Tan noted that Cadence has a 20nm solution that spans both custom/analog and digital design, but for this webinar, the focus was on digital design using the Cadence Encounter Digital Implementation System. The following slide depicts the Encounter 20nm RTL-to-GDSII methodology.

To illustrate DPT (double patterning) aware placement, Tan provided an example. The layout decomposition process uses two different colors to indicate which layout features go on which mask. If you place two cells close together, and adjoining edges have the same color routes, a DPT violation is likely to occur. One way to resolve it, as shown below, is to insert some dummy space between the cells. Another is to flip one of the cells to its mirror image.

FlexColor DPT routing in the NanoRoute router uses a correct-by-construction approach that obeys new 20nm design rules, including double patterning rules, Tan said. The user doesn't need to ensure that each route is DPT correct. Moreover, the approach improves area efficiency and allows effective ECOs.

Tan talked quite a bit about extraction, and noted how the Cadence QRC extraction engine (available both standalone and through Encounter) has been beefed up for 20nm. QRC can handle new 20nm modeling considerations such as raised source drain with bias and via/local interconnect resistance. It can also take into account capacitance variations that occur with slight mask misalignments during double patterning. These are modeled with multi-valued Standard Parasitic Exchange Format (SPEF) files, which in turn can be read by the Encounter Timing System and Encounter Power System.

Finally, Tan discussed the Cadence Physical Verification System, which can provide a "golden" signoff timing check. The engine is also integrated into the Encounter Digital Implementation System. "We use the same engines in our implementation tools as we use in our signoff tools, so you get no surprises as you go from implementation to signoff," Tan said.

Samsung-Cadence Collaboration

Lin briefly described the "logic test vehicle" that Samsung and Cadence developed in 2011. It included an ARM Cortex-M0 macro and a 32K SRAM macro. "This is how we prove and trail blaze our technology," he said. "In addition, Cadence and Samsung are embarking on collaboration on double patterning, so we're working very closely together."

"Cadence and our industry partners have been investing very heavily in 20nm," Tan said. "We do believe that close partnerships between foundries, IP providers and EDA vendors will pave the way for smoother adoption of advanced process nodes including 20nm."

The archived webinar is available here.

Richard Goering



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