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Cadence, ARM and TSMC Reveal 20nm Challenges and Solutions

Comments(0)Filed under: EDA, Industry Insights, ARM, DFM, Encounter, EE Times, Double Patterning, TSMC, Cortex-A15, variability, static timing, Cadence, extraction, FlexModels, 20 nm, PPA, physical IP, ccopt, Desharnais, clock concurrent optimization, LDE, GigaFlex, variation, mask misalignment, test chips, giga-scale, mask shifts, Chong, Quan, 20nm webinar

At a recently archived EE Times webinar May 1, representatives of Cadence, ARM and TSMC noted three important points about the 20nm process node. Number one, its adoption is inevitable. Number two, the design and manufacturing challenges are significant. Number three, the challenges are manageable given the right tools and methodologies, and solutions are becoming available now.

The webinar was titled "Industry Leaders Unveil Shared Vision for 20nm." It was followed by Cadence webinars May 2 (on digital 20nm implementation) and May 3 (on custom/analog 20nm implementation). The May 1 EE Times webinar included the following speakers:

  • David Desharnais, group director, Silicon Realization Group, Cadence
  • Tom Quan, deputy director of design methodology and service marketing, TSMC
  • YK Chong, senior principal engineer, Physical IP Division, ARM

Around 400 people registered for one or more of the webinars, and they answered a few questions as they did so, making for some interesting findings. Around 32% are working at 28nm today, 14% are working at 20nm, and 20% are using a mix of these two process nodes. Of those not yet at 20nm, 70% said they expect to be doing 20nm design in the next 6-12 months. "You can see there's a pent-up desire and demand to drive to 20nm," Desharnais commented.

There's good reason for that. According to Desharnais, the 20nm node can provide 2X the gate density, 20% better performance, and 25%-30% lower power than the 28nm node. These capabilities will help enable and differentiate the next generation of mobile devices. "But none of this comes easily," Desharnais said. "We can help you get down that path, but there are some things you need to know."

Tom Quan of TSMC - The Foundry View

Quan cited a similar value proposition for 20nm. Compared to 28nm, he said, it can offer a 2X gate density improvement, 20% better performance at Vdd=0.85V, and 25% switching power reduction at the same speed. Multiple threshold voltage (Vt) and long gate (Lg) options extend the performance envelope further.

However, double patterning -- which splits metal layers into two masks - is necessary to overcome the limits of lithography at 20nm. But TSMC is making it easier with its "G0" rule, which helps validate whether a layout is separable, or decomposable, into two masks. The G0 rule can detect and help fix potential violations, and it works with EDA tools from Cadence.

Layout decomposition is indicated by assigning different colors to patterns that will be made by different masks. However, Quan said, "most of the time you don't have to worry about coloring. The tools from Cadence will be able to decompose the layer into two different masks and assign colors itself." However, there are cases where designers might want to place high-speed nets or differential pairs on the same mask. In this case a manual "pre color" process is available - and design rules will make sure it's done correctly.

Design for manufacturability (DFM) is also a big concern at 20nm. Quan described a 20nm DFM solution that avoids critical patterns (CPs), uses CP-aware routing and wire spreading, and then uses design rule checking that allows users to clean up potential yield problems. Another challenge is RC extraction, which must account for additional variation from the possible misalignment of masks. This results in more corners than currently exist at 28nm.

Additional RC corners means more static timing analysis runs, and traditional static timing methodologies are no longer accurate enough to analyze pattern shift (mask misalignment) effects in a single run. "The solution we're working on with Cadence is to create a multi-value SPEF [standard parasitic exchange format] file so we can achieve double patterning signoff accuracy and eliminate excessive static timing analysis runs," Quan said.

Quan concluded by talking about the importance of early engagement with EDA partners, and the importance of 20nm EDA tool certification. 20nm engagements started with a V0.01 design rule manual, much earlier than previous process nodes, and now TSMC is working with partners to come up to "V1.0 maturity" - and Cadence, Quan said, has "completed phase one certification as of today."

Dave Desharnais of Cadence - The EDA View

Since 2009, Desharnais said, Cadence has been making serious investments in 20nm. To date, Cadence has collaborated on 12 20nm tapeouts, with 13 more in progress. "We've been able to put together a flow that includes foundry and ARM qualification, and we have libraries, PDKs and rule decks," he said. "This is coupled with the work we're doing around IP, where we're building high-performance interfaces. We also have 20nm mixed-signal IP that will be pre-integrated with the digital controller, the drivers, and the package and board."

Desharnais said that most of the test chips use ARM processors and many of the customers are in the mobile market. "We've learned a ton," he said. One discovery is that mask shifts can add 10%-15% timing variation, and this is something that needs to be analyzed rather than patched up with guardbands.

Desharnais identified three "success factors" at 20nm - manufacturability/variation, "giga scale" design productivity, and power, performance and area (PPA) optimization. According to the pre-registration survey, manufacturability and variability are the key concerns for the webinar audience. This includes double patterning and the explosion of new layout rules, resulting in some 5,000 design rule checks at 20nm.

For the digital designer, Desharnais said, double pattering is done automatically. However, "you need to comprehend it, you need to understand the variation that occurs as a result of it, and you need to understand things like mask shifts and how they impact timing variation." He noted that the Encounter Digital Implementation System is "completely double patterning aware" throughout placement, optimization, clock tree synthesis, routing, extraction, and physical verification.

In the custom/analog world, automatic colorization is driven by constraints. "We worked closely with TSMC to embed that intelligence into our software," Desharnais said. Another big issue for custom/analog designers at 20nm is layout dependent effects (LDE), due to effects such as stress, shallow trench isolation, length of diffusion, and well proximity effect. Cadence has built an understanding of LDE into its Virtuoso custom design solution, which can generate rapid prototypes and provide early layout information that lets designers resize circuits.

A second success factor is "giga scale" design productivity. At 20nm, digital designers are dealing with 100M-plus instance designs and partitions with several million instances. This can easily choke the tools. GigaFlex is a new modeling technology, available in the Encounter 11.1 release, that can provide just the right level of detail that's needed at any given level of abstraction. Desharnais told of placements that normally take 15 hours taking only a little over 1 hour with GigaFlex FlexModels.

On the custom/analog side, Cadence is attacking complexity with semi-automated techniques such as the rapid prototyping mentioned earlier. In-design signoff verification is another important technique. But the "real magic," Desharnais said, comes with the Cadence mixed-signal solution, which is built on the OpenAccess platform. This is key because all 20nm SoCs will be mixed-signal SoCs.

The third success factor is PPA optimization. Here, Desharnais talked about clock concurrent optimization (CCCopt), a new technology available with Encounter 11.1 that integrates timing-driven placement, clock tree synthesis (CTS), incremental logic sizing, and post-CTS optimization into a single step. Results have included a 48MHz performance gain, a 10.4% clock power savings, and a 31% clock area savings, all without trading off one versus the other.

YK Chong of ARM - The IP Provider View

Chong noted that ARM has "invested a lot of resources to ensure the SoC designer has a smooth transition to 20nm." On the physical IP side, this includes high-density and high-performance architectures, multi-Vt and multi-channel devices, a comprehensive set of standard cells, and a rich set of memory types, performance and size ranges. The alpha release of a complete set of physical IP for TSMC 20nm is planned for the second quarter of 2012 for lead partners.

Chong spoke about the importance of early collaboration, and he noted that ARM, Cadence and TSMC successfully taped out the first Cortex-A15 20nm test chip in September 2011. Built on the TSMC N20G process, it includes a single CPU with 32KB L1 cache, 512KB L2 cache, and 2 million instances. The chip "trail blazed and optimized" the 20nm design flow and provided valuable information for process debugging, he said.

Chong's list of key 20nm challenges included metal pitches reduced to 64nm, accurate delay modeling, increased wire resistance, double patterning, signal integrity, electomigration, and increasing variability.

"20nm introduces many new challenges for SoC implementation," Chong concluded. "Early collaboration between foundry, IP and EDA partners is essential to address these challenges. TSMC, ARM and Cadence are addressing these challenges through the Cortex-A15 test chip. We will continue to collaborate to ensure that when the customer is ready, the processor and physical IP will be there."

The overall takeaway from the webinar? "We're ready to engage when you are," Desharnais said.

An archived version of this webinar is available here. 

Richard Goering

 

                                 

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