Reusable, commercial verification IP (VIP) has greatly eased the functional verification task for complex interface protocols. However, verification engineers still have a significant amount of manual work to perform. Cadence this week is addressing this problem by announcing the TripleCheck IP Validator, a new addition to the Cadence Verification IP (VIP) Catalog that simplifies and automates the process of verifying that IP components adhere to standard protocol specifications.
TripleCheck is an option for Cadence VIP, and it is available today for PCIe Gen3 VIP with support for more protocols coming throughout 2012. TripleCheck is integrated with the Cadence VIP PureView user interface, and it provides three main capabilities:
- Test suite - TripleCheck provides a library of test sequences, including directed tests for basic protocol compliance and constrained-random sequences that provide exhaustive testing.
- Coverage model - Pre-defined coverage models for both e and SystemVerilog capture all data items and state machine transitions in order to track and measure verification progress.
- Verification plan (vPlan) - TripleCheck provides a verification plan derived from the protocol specification. The plan is linked to the coverage model so that the coverage data captured during simulation runs is automatically mapped to the plan.
These capabilities were available separately in PureSuite and the Compliance Management System (CMS), both offered with Cadence VIP. TripleCheck now combines the three elements plus additional ease of use features.
What's Missing Today
VIP components do a lot of heavy lifting for the user by providing a bus-functional model, monitor, and other essential capabilities, but the verification engineer still has to create coverage groups and define test scenarios for multiple design configurations in order to complete the verification process. According to Tom Hackett, product marketing manager for VIP at Cadence, the engineer's first challenge is to set up a wide range of parameters to configure the VIP to match the design. Since a complex protocol like PCI Express may have over 100 different parameters, this is not an easy task. Mistakes are commonplace and errors may take days to find.
The next challenge, at least for a new design, is to create hundreds or thousands of tests. While constrained-random testing means that engineers don't have to create as many tests, there's still a role for directed tests, Hackett said. "What we've learned is that certain basic protocol behaviors are more quickly verified by directed tests," said Hackett. "On the other hand, exhaustive corner case exploration is best done with constrained random test sequences. It's most productive when both approaches are intelligently applied according to the challenges of a given protocol."
As the tests are run, simulation produces huge amounts of coverage data, with perhaps tens of thousands of coverage points. Engineers must now go through this massive database and figure out what the data means and how it links back to the specification they're trying to verify. In the case of PCIe Gen3, this coverage data has to be mapped to a thousand-page spec.
"There's still a lot of manual work," Hackett observed. "The unique thing about TripleCheck is that it stitches together this whole flow."
TripleCheck -- A Better Way
Hackett revisited the protocol verification flow using TripleCheck. First, instead of manually configuring hundreds of parameters to capture the design configuration within the VIP, the engineer uses the PureView GUI to configure the VIP. PureView automatically makes sure there are no illegal combinations. PureView outputs a user configuration file that can be used to bring up previous test setups.
Secondly, TripleCheck provides both directed and constrained-random tests. Working with PureView, TripleCheck can configure the test suite to match the device under test. "That's a time saver that nobody has done before," Hackett said. The test suite can run on any major simulator.
Finally, TripleCheck outputs native e and SystemVerilog coverage databases. These databases can be linked to the vPlan in Incisive Enterprise Manager, and they also can be read by other simulation environments, including Synopsys VCS and Mentor Graphics Questa. Users of those products can then use whatever tools they have to analyze the coverage data.
Going forward, Hackett said, TripleCheck will replace PureSuite in Cadence VIP. CMS, however, will be retained for those VIP components that have it now. Cadence VIP for any new protocols will include TripleCheck support. Further information is available here.