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Q&A: 7 Years After Verisity – How Specman and e Language Changed IC Verification

Comments(0)Filed under: Industry Insights, TLM, specman, Accellera, OVM, verification, Metric-driven verification, Functional Verification, Verification IP, Simulation, VIP, UVM, MDV, SystemVerilog, Cadence, e language, eRM, IEEE 1647, coverage-driven verification, verification reuse, Axis, UVM-e, IC verification, igen, Specman/e, Eliopoulos, Gavrielov, Verisity, IntelliGen, aspect-orieinted programming

Seven years ago this month (April 2005) Cadence acquired Verisity, the pioneering verification company that developed the e language and the Specman environment. The acquisition resulted in a paradigm shift in IC verification, setting the stage for reusable verification methodologies, constrained-random testbench generation, metric-driven verification, and significant use of verification IP (VIP). Today Specman technology is integrated into the Incisive verification family and the IEEE 1647 e language is in widespread use.

In this interview Andy Eliopoulos, vice president of R&D for Advanced Verification Solutions at Cadence, reflects on how the Verisity acquisition changed the Cadence culture, the advancements in verification technology, the connection between Specman and the Universal Verification Methodology (UVM), and the continuing use of the e language for verification. He also strongly reaffirms the Cadence commitment to full support for Specman/e.

Q: Andy, how has Cadence changed as a result of the Verisity acquisition?

A: Before April 2005 Cadence and the industry were mainly focused on simulation. We really didn't have a verification methodology that was adoptable by the industry. We brought in the Verisity team because they had a 100% focus on verification. They had a testbench language with a reuse methodology, a solid collection of VIP, and a coverage-driven verification methodology.

Since the Verisity acquisition, we have been investing in the unification of the Verisity technology into the Incisive Enterprise Simulator. Today, we deliver solutions with advanced verification testbenches using both SystemVerilog and e. We transitioned from coverage-driven verification to a more advanced, verification plan-based, metric-driven verification [MDV] solution. Just like the progression from eRM to OVM and now UVM, the MDV methodology originated and was prototyped with e.

Q: What key benefits did the Verisity acquisition bring?

A: Number one was people. Verisity brought in verification expertise we did not have. Moshe Gavrielov [Verisity CEO] ran the verification division for four years. The acquisition also brought in people like Ziv Binyamini [VP for R&D for System Solutions Group], Erik Panu [VP for R&D for VIP], and Mike Stellfox [Cadence fellow]. Also, the Verisity FAEs were very critical in moving customers from just running simulation to having a verification methodology. At the time, other vendor FAEs had little verification expertise. Many of the leaders from the Verisity team rose to leadership roles within Cadence to drive the overall verification group.

A second key benefit that Verisity brought to Cadence was the overall Specman/e verification technology. Incisive® Enterprise Specman® products give users the industry's most powerful capability for automating the process of verification -- automatic generation of functional tests, data and temporal checking, functional coverage analysis, and so forth. Specman uses aspect oriented programming (AOP) while SystemVerilog and SystemC use object oriented programming (OOP). For verification engineers, AOP makes it easy to write and run efficient tests, and to reuse verification environments from block to system and from one project to another. AOP thus makes e a much more productive verification language.

Third, Verisity brought the eRM [e Reuse Methodology] concepts to Cadence. As most readers may know, OVM-e was the next generation of the Verisity eRM, which now has evolved into UVM-e. Cadence has uploaded the UVM-e reference flow to the UVM World contributions site. Developed by Cadence, UVM-e applies the Universal Verification Methodology to e. The sample verification environments contain UVCs based on eRM as well as UVM-e. Both eRM and UVM-e compatible UVCs can be nicely integrated together and can work seamlessly.

Q: What key technology did Cadence acquire?

A: Verisity's leading product was Specman, which provided the ability to build an advanced verification testbench. This approach included a high-capacity constraint-solving engine coupled with functional coverage. The methodology on top of that was eRM. With this methodology customers were able to find bugs in their Verilog, VHDL, SystemC, or SystemVerilog designs caused primarily by ambiguities in the spec, or unanticipated usage by the target system. The result? Faster verification and higher quality products. Since then, this methodology has been the basis for OVM and UVM.

Also, Verisity acquired Axis acceleration technology in 2004. The Axis simulation acceleration products were sold by Cadence for many years.  Key Axis technical people are still contributing to Cadence products.

Q: How did Cadence improve Specman technology after the acquisition?

A: Much of the IntelliGen [constraint solving engine] was developed under the Cadence leadership. Recent enhancements include the Specman Advanced Option, which improves simulation runtime and regression throughput by enabling reseeding capability, and reloading a constraint random testbench without having to return to time zero.   This year we are rolling out new debug technology, which will improve debug productivity by analyzing the environment from a flow perspective and automated go-to-cause capability.

Q: Verisity came into Cadence with coverage-driven verification. What's the difference between coverage-driven and metric-driven verification?

A: With the coverage-driven approach you run your simulation, look at things like functional coverage or code coverage, and get a grading on whether you've achieved 100% coverage or not. With metric-driven verification, the specification defines what the DUT [device under test] should be doing, and that turns into metrics that involve multiple pieces of coverage. After a coverage simulation, the results are merged and correlated to your actual specification. Metric-driven methodologies take your verification to a higher level of abstraction.

Q: How did Specman lead to UVM?

A: Specman came out in the mid-1990s and created the idea of a verification reuse methodology. Fundamentally, e was based on aspect-oriented programming concepts and provides for reuse of verification components. The Verisity team invented the eRM and the eRM became the ground work for what we developed as the Open Verification Methodology (OVM) that went into the standards process and, with contributions from other companies, became UVM.

Q: The current Accellera UVM standard, however, only works with SystemVerilog. How does UVM work with e?

A: When we developed OVM we developed an architecture that allows it to support all relevant class-based languages - e, SystemVerilog, SystemC. The underlying architecture of UVM already supports multiple languages. We can support e, SystemVerilog, and SystemC in UVM today. As explained previously, the Cadence donation of the UVM-e reference flow is an excellent proof of how the eRM and UVM-e compatible UVCs can be nicely integrated together and can work seamlessly. [Note: For more details about this multi-language support, see the recently published Advanced Verification Topics book].

Q: How would you describe the adoption of Specman and e today?

A: Specman and e based customers are a significant portion of our verification revenue stream. There is a large and extremely loyal customer base. It's a huge differentiator for us. We've had some significant wins in the past two years, including customers who are going from SystemVerilog back to e because they realized e was more productive than SystemVerilog.

Q: Is Cadence still committed to the long-term support of e?

A: Cadence is fully committed to supporting e and to continuing our investment in e. You will see evidence of that in the Cadence portfolio of products that are being delivered to the marketplace this year. Roughly a third of our division's development team is still located in Tel Aviv [former Verisity office].

With Incisive we are providing a platform that connects you to whatever language you want to use, and not just e and SystemVerilog, but also VHDL and Verilog. Almost all of our top verification customers are using the Specman/e solution because of its ongoing effectiveness to handle the giga-gate designs they are developing today. Many customers have evaluated both SystemVerilog and e languages and have chosen to stay with e because it excels in speed, ease of use, coding efficiency, scalability, and verification throughput.

Q: What's on the horizon for the next 7 years?

A: It's wide open. There's a lot of work to be done in the SoC verification space, as we see customers move to designs with well over 100 million gates. This puts all kinds of stress on software-based verification. We're looking now towards what we can do in the systems space by using different levels of abstraction and hardware-based systems like Palladium. We're seeing more usage of high-level synthesis and TLM modeling.

One key message is that the e language is alive and vibrant and is going to play a significant role in the verification market. For advanced verification users, e is the best solution, and that is also reflected within our customer base. A majority of our advanced verification customers use e as their verification language of choice. In addition to our commitment to e, we will continue to leverage the cumulative verification expertise that we inherited from Verisity to ensure that our Incisive verification solution is also the best solution for SystemVerilog and SystemC.

Richard Goering

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"Advanced Verification" Book Brings UVM to Mixed Signal, Low Power, Multi-Language

User View: Is e or SystemVerilog Best for Constrained-Random Verification?



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