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System-Level Low Power Design – What Will it Take to Move There?

Comments(0)Filed under: Industry Insights, ESL, low power, High-level Synthesis, HLS, UPF, CPF, Power, EDP, emulation, embedded software, Gary Smith, software, power management, system-level, system level, Palladium XP, ChipEstimate.com, Wang, power optimization, chip planning, EDP 2012, EDPS, Qi Wang, dynamic power analysis

While many low-power design techniques are available to IC designers, the greatest potential for power savings is at the system level, where both software and hardware can be considered. So what's standing in the way of system-level low power design, and what needs to happen to make it practical? Qi Wang, group director for solutions marketing at Cadence, provided some answers in a recent talk at the Electronic Design Processes Symposium (EDPS 2012) in Monterey, California.

The presentation was titled "Low Power Design: Is the Problem Solved?" Wang started his talk by noting that power requirements have different drivers in different vertical markets. In the mobile area, the concerns are battery life and cost; in data centers, the concerns are power efficiency and cost of ownership.

"Ideally, I want to do low-power designs from the architectural level down to silicon in a very predictable way," he remarked. "In order to save power, software is king." But what really happens, he said, is more like the chart shown below. There is little visibility during system design. There's no good way to correlate RTL with the final silicon power. Integrating multiple IP blocks from different sources will change the estimation and disrupt the design flow. Finally, if real software doesn't run until silicon is available, many potential power gains can be lost.

There is some good news. Low-power design flows weren't automated 5 years ago, and there was no way to state power intent in a consistent way throughout the flow. Today, with power intent formats including Common Power Format (CPF) and Unified Power Format (UPF), there is a way to express and convey intent throughout the low-power flow.

Further, there are a number of popular low-power design techniques at the hardware level. These include power shutoff (PSO), dynamic frequency and voltage scaling (DVFS), adaptive voltage and frequency scaling (AVFS), multi-supply voltage (MSV), and adaptive body bias. The catch: all of these techniques have a high impact on the design flow.

Linking Software to Silicon

So what's next? "To attack power, software is the first step," Wang said. "However, there is a link between the software and the silicon. Software provides a higher level of abstraction for management and control - you shut off this block, you reduce this frequency. The challenge is that, if the decision you make at that [software] level is not well correlated to silicon, you make the wrong decision."

Thus, the first problem we need to solve is to correlate software and silicon, and to bring forth the accuracy that's needed to make good decisions at the systems level. "There is a huge gap between the accuracy you need and the information that's available at the software level," Wang said.

He suggested three ways to close that gap:

  • Power exploration through early chip planning, leveraging tools such as the Cadence Chip Planning System and the IP catalog at ChipEstimate.com.
  • Transaction-level modeling (TLM) IP power estimation and optimization through high-level synthesis tools that can drive power, performance and area tradeoffs, such as Cadence C-to-Silicon Compiler.
  • Dynamic power analysis of SoC and/or software using the Cadence Palladium XP emulation system. The Palladium XP can "run the software and tell you exactly where the power goes."

A lot of the potential power savings occurs through software control, Wang noted - for example, the software could shut down or speed up a processor. Emulating this behavior on a hardware platform will result in an accurate power estimation. If software does not "do a good job," then low-power techniques like power gating may not actually save power or, at best, won't operate with maximum efficiency.

In conclusion, Wang said that "power is not a silicon problem. It's not a software problem. It's a whole system problem. We have to look at the problem with a holistic approach. We want a design methodology that's repeatable, scalable and predictable." Wang's presentation is available here.

Note: Wang's talk was part of a session organized by analyst Gary Smith, who opened the session with a chart showing where improvements in SoC power consumption will come from through the year 2026. A recent EDA30 Insider blog post takes a detailed look at that chart. Another EDA30 Insider post reviews Wang's talk. See the list below for other Industry Insights and EDA360 Insider posts from EDPS 2012.

Richard Goering

Previous Blog Posts from EDPS 2012

Industry Insights "EDA Symposium: Users Cite 3D-IC Design Tool Needs"

Industry Insights "EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs"

Industry Insights "Panelists: What Needs to Happen for 3D-IC TSV Success"

Industry Insights  "Is System Modeling the Next EDA Abstraction Level?"

EDA360 Insider "Want a peak at a possible Qualcomm 3D IC roadmap?"

EDA360 Insider "3D preview from EDPS: Qualcomm's Director of Engineering Riko Radojcic talks 3D and 3D EDA"

EDA360 Insider "3D Thursday: A funny thing happened to me on the EDPS 3D-IC Panel"

EDA360 Insider "Software development for SoCs requires "bespoke" software enablement platforms"

EDA360 Insider "Jim Hogan's top six SoC trends for 2012. Want to know what they are?"

Denali Memory Report "A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth-per device"

 

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