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Is System Modeling the Next EDA Abstraction Level?

Comments(0)Filed under: EDA, Industry Insights, ESL, RTL, High-level Synthesis, HLS, TLM, virtual platforms, IP, Electronic Design Processes, EDP, embedded software, Gary Smith, integration, SysML, software, system-level, system level, SoC: EDA360, UML, modeling, prototyping, hardware/software integration, software development, Schirrmeister, EDPS, transaction level, Ptolemy, models of computation, Mathworks, system modeling, MoC, SDKs

According to a recent talk by Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, the answer is "yes." System modeling is a level of abstraction that's independent from hardware and software implementation. But there are some interesting questions -- who will do this modeling, who will build the models, and how can the EDA industry contribute?

Schirrmeister spoke at the Electronic Design Processes Symposium (EDPS) April 5, 2012 in Monterey, California. His talk was titled "System-Level EDA 2015: Whose Problem is Software Anyway?" He started his talk with a big number: $2.74 trillion. That's what the electronic systems market is expected to grow to in 2016. This includes a $517 billion semiconductor market and a $2.1B semiconductor IP market - and a great deal of software.

So whose problem is software? Both hardware and software roles have shifted over the past decade. Software development providers have played a big role in platforms such as Texas Instruments OMAP. Apple acquired a semiconductor design capability, and Google recently bought Motorola Mobility. "Who's doing software in the stack has changed significantly over the years," Schirrmeister observed.

Providing Software and Hardware

Suppose the network providers decide there is a need to provide NFL football coverage on cell phones. That results in requirements that get pushed down into the design chain, impacting software and hardware. One result is that "the whole software stack becomes something the semiconductor provider, in many cases, has to provide with the silicon. They can't necessarily get more money because they have to put software in the chip - they simply have to do that," Schirrmeister said.

System vendors own the user experience, which is driven by software "apps." Hardware platforms consolidate around applications, and software changes the hardware/software development process. As a result, "hardware and software get closer together. This is really the driving factor in EDA, the need to consider hardware and software together much more closely," Schirrmeister said.

This closeness is reflected in the current move to transaction-level modeling (TLM), a technology that gives rise to virtual platforms and high-level synthesis. But what's beyond that? The next level of abstraction is neither "hardware" nor "software." It is hardware and software independent level called "system modeling." This is not a new idea - in fact, Schirrmeister reused the following slide from a presentation in 2002:

What we find at the system modeling level is a variety of models of computation (MoC). These may come with commercial tools from providers like The Mathworks and National Instruments, academic projects like Ptolemy, or standards like the Universal Modeling Language (UML) or its cousin, SysML. System modeling flows downwards into software development, hardware IP development, and hardware SoC integration. But there's a problem. "A nightmare for our customers is how they create models for all these levels of abstraction, how they validate them, and then ECO management is a big issue," Schirrmeister said.

Listening to Schirrmeister, I recalled a 2011 Industry Note from analyst Gary Smith that spoke of a new class of electronic system level (ESL) engineers who tackle the modeling of a proposed system and do the what-if analysis required to come up with the optimal design. It's not "hardware," it's not "software," it's "modeling" (you can read my blog commentary here).

The Chips of 2015

Higher levels of abstraction will be needed for the types of chips Schirrmeister anticipates for 2015. Some of these chips will have over 110 IP blocks, making system integration a huge issue. More than 70% of the content will be reused, and more than 60% of the total effort will go into software. Chips will be multi-core and low power, and have significant analog/mixed-signal content. However, Schirrmeister said, "it is not 100% clear who is doing what component of the software - it's a very entangled design chain."

Schirrmeister, who manages the Cadence System Development Suite, also noted that "no one size fits all" when it comes to software development platforms. He showed why a range of platforms is required, including software development kits (SDKs), virtual platforms, RTL simulation, acceleration/emulation, FPGA prototyping, and silicon prototyping. (For more details on this part of the presentation, see Steve Leibson's EDA360 Insider blog.)

Most immediately, Schirrmeister said, the EDA industry needs to develop a TLM methodology that will allow models to be used for both verification (virtual platforms) and implementation (high-level synthesis). "Next up is the system modeling space," he said. "It will be very interesting to see who will be serving this next-level market, this hardware-software independent piece, in the next 5 to 10 years. We are going up into this market and we had better figure out some good co-existence with the existing players."

Richard Goering

Previous Blog Posts from EDPS 2012

Industry Insights "EDA Symposium: Users Cite 3D-IC Design Tool Needs"

Industry Insights "EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs"

Industry Insights "Panelists: What Needs to Happen for 3D-IC TSV Success"

EDA360 Insider "Want a peak at a possible Qualcomm 3D IC roadmap?"

EDA360 Insider "3D preview from EDPS: Qualcomm's Director of Engineering Riko Radojcic talks 3D and 3D EDA"

EDA360 Insider "3D Thursday: A funny thing happened to me on the EDPS 3D-IC Panel"

Denali Memory Report "A possible roadmap for Wide I/O that leads to 2Tbps of SDRAM memory bandwidth-per device"

 

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