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EDA Symposium: How Wide I/O is Driving 3D-ICs with TSVs

Comments(0)Filed under: Electronic Design Processes, EDP, 3D, TSV, memory, DRAM, 3DIC, 3D IC, 3D-IC, Cadence, JEDEC, Greenberg, memory controller, wide i/o, 2.5D, BIST, LPDDR3, Wioming, ST-Ericsson, EDPS, wide-io, silicon interposer, Marc Greenberg, CAE-LETI, wide io

Any new technology needs a driving force or "killer app," and 3D-ICs with through-silicon vias (TSVs) are no exception. By allowing a high-bandwidth, low-power connection between CPU and DRAM, the new JEDEC wide I/O mobile DRAM standard will be that driving force, according to Marc Greenberg, product marketing director at Cadence.

Greenberg spoke at an all-day 3D-IC session at the Electronic Design Processes Symposium (EDPS) April 6, 2012. I blogged previously about opening talks by Riko Radojcic of Qualcomm and Arif Rahman of Altera. Greenberg's talk was titled "3D-IC is Now Real: Wide I/O is Driving 3D-IC."

The current wide I/O DRAM standard specifies 4 128-bit channels, providing a 512-bit interface to DRAM. It uses a 200 MHz single data rate (SDR) and provides 100 Gbit/s bandwidth. Current expectations are that it will provide close to a 50% power reduction compared to LPDDR3, the next-generation mobile DRAM standard, in a dual-channel configuration. Greenberg noted that future wide I/O standards are expected to provide faster data rates and may boost bandwidth to as high as 2 Terabits/second.

Greenberg said that wide I/O "gives us an amount of bandwidth that we're totally unaccustomed to having between CPU and DRAM, and gives us the capability to introduce all kinds of new applications and tools and 3D video and all the things we would want in our next generation devices."

Why TSVs?

TSVs offer the best way - and really the only practical way - to provide a 512-bit interface to DRAM in a mobile device. "We definitely see TSVs as a method of getting faster, denser, and lower power interconnect," Greenberg said. With TSVs you get a substantial increase in bandwidth between two dies, a lower power interface, and probably reduced area, given that 40% of a CPU die may be taken up by the memory controller and cache.

Greenberg looked at other alternatives, including:

  • Putting everything on one "giant" die. This is extremely difficult and costly, and because DRAM is manufactured on low-cost processes, it is generally not economically feasible to put it on chip.
  • Designing a system-in-package (SiP). It's an improvement over one large die, but you still have connections over long wires with a lot of inductance, and limited speed gains.
  • Connecting two ICs on a printed circuit board. Today, the most common way to connect CPU and DRAM is over parallel lines on a PCB, but increasing the bandwidth requires a large number of pins.
  • Serial connection on a PCB. This requires fewer pins, but has power and latency costs.

And this list brings us back to TSVs, whether in a 2.5D configuration with a silicon interposer, or in a true 3D logic-to-memory stack. With TSVs, Greenberg noted, the average number of connections between two dies goes up 10X compared to chip-to-chip connections on a PCB, capacitance improves 6X, average connection length improves by 200X for 3D stacking vs. side-by-side stacking, and relative interface power between the CPU and DRAM provides about a 6X improvement.

A Case in Point

To illustrate the use of wide I/O in a 3D-IC logic-and-memory stack, Greenberg discussed the recent Wioming test chip developed by CAE-LETI, ST-Ericsson, and Cadence. This is a heterogeneous 3D stack that includes two identical logic SoCs with TSV interconnects, uses a Cadence wide I/O memory controller, and employs a novel 3D asynchronous network-on-chip architecture. Cadence Virtuoso and Encounter tools were used to design the chip, and the tapeout was announced in December 2011.


3-die stack with memory stacked on two SoCs

While Cadence could have gone for a simple wide I/O controller for this test chip project, "we decided to go for a full implementation from the very beginning," Greenberg said. "We wanted to implement the highest performance and lowest power controller we could, so that's what we did." Additionally, Cadence modified its built-in self test (BIST) capability to include new classes of errors that may result from 3D die stacking. The Cadence wide I/O memory controller was introduced in March 2011.

Greenberg acknowledged that TSVs pose some challenges. There are questions about probing, concerns about thermal issues, and uncertainties about who will provide what in the ecosystem. Nevertheless, Greenberg said, "we have a proven silicon 3D IC solution that we've been developing in collaboration with partners for about 5 years. We have multiple test chip tapeouts. We are ready to do this."

Richard Goering

Related Industry Insights blog posts

An Update on the JEDEC Wide I/O Standard for 3D-ICs

Wide I/O Memory and 3D ICs - A New Dimension for Mobile Devices

Three Die Stack - A Big Step "Up" for 3D-ICs with TSVs



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