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ISQED Keynote: 20nm From a Custom/Analog Perspective

Comments(0)Filed under: Industry Insights, DFM, FinFets, Analog, Custom IC, Double Patterning, ISQED, variability, 20nm, custom/analog, parasitics, methodology, LDE, in-design signoff, 14nm, colorization, mismatch, Tom Beckley, layout-dependen effects, patterns, MODGEN, 10nm, Beckley

Most of the discussions about the upcoming 20nm process node have focused on digital design. Not so at the International Symposium on Quality of Electronic Design (ISQED 2012) March 20, where Tom Beckley, senior vice president of R&D for Custom IC and Signoff in the Silicon Realization group at Cadence, gave an excellent overview of the challenges custom/analog designers are facing at this emerging process node.

In a keynote speech titled "Taming the Challenges of Advanced Node Design," Beckley noted that 20nm will bring profound changes to the custom/analog world and will result in a new design methodology. At 20nm and below, he noted, "this world is changing and it is changing dramatically." No longer will circuit designers and layout engineers live in separate worlds - and circuit designers will spend a lot more time with their digital RTL counterparts, he said.

Beckley related that he recently spent time with a design team that has just finished a 20nm FinFET design for a USB PHY. Two things were learned - that parasitics and mismatches are highly problematic at 20nm, and that design complexity has "literally exploded." To get the job done, he noted, the team had 3 or 4 layout engineers for every circuit designer, whereas in the past they had 2 to 3 circuit designers for every layout engineer.

"Net net, it's a brave new world at 20nm. We're doing a lot of collaborative work to get ready but we have a long ways to go." Of the 800 people who work in his group, he said, 50% or more spend most of their time on 20nm and below. "When we moved to 28nm it was nowhere near this major a move," he said.

The Cost Challenge

Beckley observed that mobility, video, and networking are driving the move to 20nm design. The power, performance, and density improvements are compelling - some 20nm SoCs will have 30 billion transistors. But a chart that Beckley showed noted some staggering costs. While fab costs are $3 billion at 28nm, they are expected to reach $4 billion to $7 billion for 22/20nm. Design costs may reach an estimated $120M to $150M, and mask costs are expected to be $5M to $8M. "20nm is painfully expensive, and applications will need the functionality and performance to drive high volumes," he said.

Beyond cost, another challenge is manufacturing complexity, "and this is a major discontinuity at 20nm," Beckley said. One reason is that parasitics and mismatches are so severe on the analog side that circuit designers are bringing in more digital control circuitry and calibration wrappers. This is forcing analog and digital engineers to work together. Also, 20nm transistors are "very very small and very very fast," and routing and source-drain parasitics are significant challenges.

A third challenge is integrating more and more functionality onto 20nm SoCs. This means a lot more third-party IP will be needed from more sources. A complicating factor is power management, which brings with it many different power modes and "exploding" verification times.

Physical Effects

Perhaps the most-discussed new challenge at 20nm is double patterning, which splits the design into separate masks so that 193nm lithography can print structures that are close together. Beckley talked briefly about the challenges of double patterning and colorization, and showed how it's easy to create layouts that are design-rule correct but cannot be manufactured.

Beckley spent more time talking about "severe" layout-dependent effects (LDE), a phenomenon that arises because the layout context - what is surrounding a device - has an impact on the behavior of that device. This is illustrated by the following depiction of the well proximity effect. Shallow trench isolation, lithography, and stress can also cause LDE.

LDE is not something that can be modeled in PCells or device models. Yet, Beckley said, at 20nm up to 30% of the performance can be attributed to the layout context. "Physical engineers and layout engineers will find themselves drawn into the circuit designers' simulation runs in order to understand whether placement and routing causes a circuit to not perform," he said.

Beckley also talked about 400 new design rules at 20nm, new routing layers, and the advent of 3D devices such as FinFETs. "The CMOS transistor has done its duty but when it comes to low power and performance, it's running out of steam," he said. "Many foundries will continue to use planar transistors at 20nm, but some have already switched to tri-gates or FinFETs, and at 14nm we believe everybody will use these devices."

A New Custom/Analog Methodology

What's needed at 20nm, Beckley said, is a new custom design methodology. In this methodology "layout designers and circuit engineers have to work as a team. Congress is not going to design a 20nm SoC, because teamwork and collaboration are absolutely critical."

What the following diagram shows is not a conventional flow. In this new flow, a "constraint entry" step captures design intent. That intent drives placement, routing and estimation engines. A pre-layout parasitic estimation occurs early in the flow. MODGENs, or Module Generators, are not new, but in a 20nm flow they have to understand new local interconnect rules, double patterning, and LDE. Finally, real-time "in-design signoff" occurs during, not after, the design process.

"This is a journey and things are unfolding," Beckley noted. "Design rule manuals and PDKs are all changing. We're adapting as foundries adapt their processes." Indeed, several open questions remain. Should colorization be done during the design phase or handed over to the foundry? (Beckley leans towards "design.") Should pattern matching include "good" patterns as well as bad patterns, even though this may require a huge pattern library?

Even though 20nm is still evolving, Beckley concluded, "test chips are being done and designs are getting out." The Cadence custom group is working with design teams on a number of 20nm test chips, he said. Additionally, "a lot of work is going on at 14nm and we're already doing research and working with partners at 10nm."

For a review of a more digitally-oriented talk on 20nm and 14nm challenges, see my recent blog post from the Common Platform Virtual Technology Forum. For a more detailed report on Tom Beckley's keynote, see Steve Leibson's EDA360 Insider blog post.

Richard Goering




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