Home > Community > Blogs > Industry Insights > dvcon paper uvm ms brings metric driven verification to mixed signal socs
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

DVCon Paper: UVM-MS Brings Metric-Driven Verification to Mixed-Signal SoCs

Comments(0)Filed under: Industry Insights, DVCon, Analog, verification, Mixed-Signal, mixed signal, Metric-driven verification, AMS, UVM, MDV, analog/mixed-signal, coverage, UVM-MS, digital, wreal, analog verification, metrics, verification plan, Advanced Verification Topics, DVCon 2012, real number modeling, DVCon paper, Khan

Nearly all systems-on-chip (SoCs) are mixed-signal, and they must all be verified. While digital verification is heavily automated, analog verification is still a manual process, making mixed-signal verification extremely challenging. Can we bring digital verification technology, such as metric-driven verification and the Universal Verification Methodology (UVM), into the analog/mixed-signal world? Yes, according to a paper given at the recent DVCon conference.

The paper was titled "From Spec to Verification Closure: A case study of applying UVM-MS for first pass success to a complex MS-SoC design." It was authored by Yaron Kashai, distinguished engineer at Cadence, and Neyaz Khan, formerly of Cadence and now senior member of technical staff at Maxim Integrated Products. Khan presented the paper, noting that it discussed work done at Cadence before he joined Maxim, and that the work is further described in the recently published Advanced Verification Topics book.

(Quick background: Metric-driven verification starts with an executable verification plan, runs tests, compiles coverage metrics, and continues this process until the desired verification coverage is achieved. UVM is a standard methodology built on top of SystemVerilog -- but extensible to other languages -- and UVM-MS is an adaptation of UVM aimed at mixed-signal verification.)

Why Metric-Driven Verification for Mixed-Signal?

"Everyone knows how difficult it is to finish digital verification," Khan said. "Now throw analog into the mix and it becomes much harder." Traditional analog verification, he noted, is still an inefficient manual process in which "you have to eyeball a lot of stuff." Digital verification has seen a number of advancements, including UVM, and now it's time to bring these advancements to the analog world, he said.

But how to do that? Khan spoke of three requirements. One is to extend UVM concepts to cover mixed-signal, hence UVM-MS. New concepts include analog sequences, analog coverage, and analog checks. Another requirement is making UVM aware of analog concepts such as sampling rates, sampling windows, and trigger events. The challenge here is that analog is continuous and digital is event-driven, and the two environments must communicate. The third requirement is to extend an executable verification plan to include analog checks and metrics.

For example, an analog check might call for a sweep from 500 MHz to 2 GHz in steps of 100 MHz. You should be able to automate that check, and then ensure that all possible combinations of the cases have been covered, Khan said.

The diagram below shows the UVM-MS architecture. A UVM testbench includes source agents and monitoring agents, and with UVM-MS it would include analog signal generators and monitors. The device under test (DUT) can be modeled at any level of abstraction, including SPICE, Verilog-AMS, or real number modeling. Mixed-signal additions to traditional UVM (shown at bottom) include register setup, a programmed signal source, a programmed propagation delay, a sampling window, and coverage collection.

It's important to note that UVM-MS does not replace traditional, block-level analog IP verification. "What we want to verify is not the detailed functionality of the analog - we assume that's been done really well in the analog environment in the traditional way," Khan said. "What we're doing is adding UVM on top of that, as we bring analog and digital together." UVM-MS can be applied at both the IP and the SoC level, he noted.

A Case in Point

Khan walked through a "fictitious" design example that uses a digitally-controlled noise cancelling receiver as the DUT. He showed how to create an executable verification plan with analog coverage, map collected coverage to planned coverage, set up the simulation with real number modeling, set up and trigger analog checks, use assertion-based checkers, use a scoreboard for end-to-end checks, and analyze analog coverage. Audience members were clearly interested, asking many questions.

Khan's conclusion: "All of this works." He noted that UVM provides a reconfigurable and reusable verification environment, that executable verification plans can represent analog requirements and track coverage, that analog checks can be automated, and that analog coverage provides an impartial metric of design quality. "In the end, there's a pretty high impact on quality, predictability and productivity using this approach," he said.

Want to know more? The Advanced Verification Topics book has a detailed chapter on UVM-MS. You can read a review here or order a copy of the book here. DVCon 2012 papers will be publicly available April 20.

Richard Goering

Other DVCon 2012 Coverage

DVCon 2012: Accellera "Town Hall" Meeting Explores Future of EDA Standards

Hardware/Software Codesign: Pink Elephants on Parade?

DVCon User Panelists: Is Low Power Design Worth the Costs?

DVCon Panel: Will Differentiation Through Software Kill Chip Design?

DVCon Panel Debate - "Build or Buy" Emulation and Prototyping?

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.