If you want a deeper understanding of the challenges, trends, and potential new solutions for IC and systems design, there's no better place to find out than the IEEE-sponsored Electronic Design Processes Symposium (EDP) April 5-6, 2012, in Monterey, California. Now in its 19th year, this interactive, informal gathering in a beachside hotel brings together some of the top thinkers, movers and shakers in electronic design processes and CAD methodologies.
I have attended this symposium a number of times and have always come away with some good insights. Themes in last year's symposium included low-power design, 3D-ICs, and EDA in the cloud (see listing of blogs at end of this post). 3D-ICs continue to be a major theme this year, with an entire day (Friday, April 6) devoted to this technology.
EDP Symposium 2011
Cadence is participating in EDP 2012 with speakers in several sessions. Here's a brief review of the program as it exists at the time of this writing:
Thursday April 5
Keynote: Misha Burich, CTO, Altera on "Market drivers and technology enablers for embedded processing on FPGAs."
Top Five EDA Problems
- Sri Ganta, Broadcom, "DFT at RTL"
- Frank Schirrmeister, Cadence, "System-level EDA 2015"
- Tom Spyrou, AMD, "Parallel EDA"
- Sangeeta Aggrwal, Synopsys, "Runtime variance with NUMA architecture"
EDA in the Cloud (Hans Spanjaart, Altera, moderator)
- James Colgan, Xuropa, "The CAD-less semiconductor company"
- Don McMillen, Nimbic, "Electromagnetic simulation using HPC in a cloud"
- Kiron Pai, Intel, "Improving user productivity in a cloud environment"
- Azadeh Davoodi, U. of Wisconsin, "Highly distributed and confidentiality preserving global routing"
- Naresh Sehgal, Intel, "Optimizing a cloud with SLAs and QoS"
Low Power with Performance
- Gary Smith, Gary Smith EDA, "Low clock speed computing"
- Ian Ferguson, ARM, "Energy efficient servers for the data center"
- Qi Wang, Cadence, "Low power design - is the problem solved?"
- Grant Martin, Tensilica
Dinner Talk: Jim Hogan, private investor, on "Soc Realization: The next horizon"
Friday April 6
Keynote: Riko Radojcic, Qualcomm, "Roadmap for design and EDA infrastructure for 3D products"
3D-IC Design Flow Topics
- Steven Pateras, Mentor, "Evolving BIST solutions for 3D-ICs"
- Arif Rahman, Altera, "FPGA design challenges"
- Samta Bansal, Cadence, "Wide I/O is driving 3D-IC TSV"
3D-IC Design Panel (Steve Leibson, Cadence, moderator)
- Herb Reiter, EDA2ASIC
- Samta Bansal, Cadence
- Dusan Petranovic, Mentor
- Deepak Sekar, MonolithIC 3D
- Steve Smith, Synopsys
Early Bird Registration Expires Soon
Early registration deadline is March 18th, with fees of $280/$350/$100/$200 for IEEE members, non-members, students and unemployed IEEE, and IEEE Life Members, respectively. After March 18th, registration fees are $330, $420, $100, $295, respectively. Registration includes a copy of the workshop notes, continental breakfast on both days, lunch both days, and the EDP banquet dinner. The event will be held at the Monterey Beach Resort hotel.
Industry Insights blog posts from EDP 2011:
ARM Keynote: Some Inconvenient Truths About Low-Power Design
IEEE Workshop: Panelists Identify Requirements for 3D IC Adoption
EDP Workshop: Will Security Concerns Slow EDA in the Cloud?