In my last blog post I discussed new optimization and modeling technology in the Encounter 11.1 release, announced by Cadence March 5. While that blog post focused on physical IC ("back end") design, the new release also brings more "physical awareness" to front-end design, and that's the focus of this blog post. Information for this post was provided by Andy Lin, vice president of R&D for front-end design, and Yoon Kim, product marketing group director for front-end design.
In the Encounter 11.1 release, RTL Compiler and RTL Compiler Physical offer improved quality-of-results (QoR) for advanced ARM processors such as the Cortex-A9 and Cortex-A15. Lin explained that the number of logic transformations has doubled, and that the Cadence synthesis tools can now handle larger transformations.
Improved slew-aware modeling is another new synthesis feature. This is important because the contribution of wire to path delay increases substantially at 20nm. Due to larger via and metal resistance, slew degradation across a wire has a major impact on achieving timing closure. Front-end RTL synthesis must account for this effect to achieve the best local and global structures at 20nm. Thus, in Encounter 11.1, RTL Compiler and RTL Compiler Physical perform architecture and gate selection with improved slew-aware modeling and delay calculation throughout the front-end flow.
Synthesis has become more physical-aware through enhancements such as the following in RTL Compiler Physical:
- Structured datapath support is a way of defining the relative locations of different cells in the datapath, and driving that forward into placement to provide a faster rate of convergence and higher performance.
- Physical-aware logic structuring moves to an even higher abstraction layer, making it possible to choose, for example, the best implementation for a multiplexing function.
- Physical-aware mapping takes into account the distance of paths, which is ignored when the mapping is purely logical. It could, for example, identify two logic cones that are located far apart, and do some "re-mapping" to better meet timing.
Also, turn-around times for RTL Compiler and RTL Compiler Physical are 15% faster on average than the previous release, a capability that will be especially welcome for the larger chips that will be designed at 28nm and 20nm.
Looking beyond synthesis, the new Flatten ECO Flow (FEF) from Conformal ECO Designer helps users dramatically increase productivity when performing functional ECO design changes on hierarchical designs. It also provides better QoR. In one design, this flow showed a 10X runtime improvement and 20X QoR improvement.
Finally, a new distributed automatic test pattern generation (ATPG) engine promises an average 3.7X speedup over a network with four CPUs, or a 13X average speedup over a network of 16 CPUs. Cadence is also offering logic built-in self test (LBIST) for the first time.
Further information about Encounter 11.1 is available here.