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EDA CEOs Speak Out: 3D-ICs, IP Integration, Low Power, and More

Comments(1)Filed under: Industry Insights, EDAC, ARM, low power, TSVs, 3D ICs, Power, CEO Panel, EDA Consortium, Lip-Bu Tan, stacked die, mechanical, EDA360, software, Segars, Cadence, Mentor, De Geus, Rhines, Synopsys, IP integration, SoC Integration, China, Tan, education, startups, EDA CEOs, CEOs, EDA forecast, Gradient, growth, Cheng, CEO forecast, 3D-ICs

What's driving the EDA industry today and where is it headed in the near future? Some high-level answers to these questions came from the EDA Consortium (EDAC) annual CEO Forecast panel Feb. 29, 2012. EDA industry leaders shared their views about 3D-ICs, SoC integration, power management, industry growth drivers, the structure of the EDA industry, and the geographical location of design work 5 years out.

As in previous years, the panel included CEOs of the three largest EDA companies - including Lip-Bu Tan (Cadence), Wally Rhines (Mentor Graphics), and Aart de Geus (Synopsys). It also included Ed Cheng, CEO of Gradient Design Automation, and Simon Segars, executive vice president and general manager for ARM's Physical IP division. All of the panelists serve on the EDAC Board of Directors.

The panel was moderated by Ed Sperling, editor-in-chief of the System-Level Design community of Chip Design Magazine. The format was very different from previous years, when each panelist gave a presentation. Instead, questions were posed in advance to the EDAC membership and the CEOs. Sperling then compared the answers from EDAC members and the answers from the CEOs, and based his questions on those answers.

Here are some of the key takeaways from the panel discussion.

1.  3D-ICs with TSVs won't become "mainstream" for several more years.

Sperling noted that both EDAC members and the CEO panelists predicted that 3D-ICs with through-silicon vias (TSVs) will not become mainstream until 2015-2016. Comments such as the following reinforced that view.

Rhines: The idea that you will stack multiple logic die and put TSVs in the active array is something that has a whole lot of challenges with insufficient incremental benefit. I'm betting that people will go with the more cost-effective benefits of silicon interposer, stacked memory, and memory on processors long before we go with stacked logic.

De Geus:  If you do any of this with multiple players and something doesn't work - it's his fault, it isn't my fault! Right there the debate goes off the deep end. The only positive I can see is that you can put heterogeneous systems together more easily.

Tan: Cost is an issue - TSVs are expensive. The other thing is who takes responsibility if there are multiple players and something goes wrong. We are waiting to see who will drive it [3D-ICs]. It's going to be a very interesting dynamic.

Cheng: Stacking logic and logic will be quite challenging, but we have tools that can help solve that problem. What happens with the assembly and supply chain is more challenging.

2.  IP/SoC integration is still a tough challenge.

In response to a pre-panel question, CEOs identified "integration" as the key challenge in IC design, whereas EDAC members noted concerns about software, power, cost, and time-to-market as well.

Sperling: In the world of IP people thought we would go with a Lego [assembly] approach, but it doesn't go together that easily. Will we see larger Legos?

Segars: I think bigger Legos are inevitable. But there are a million ways you can put your chip together and a million and one ways to get it wrong. The biggest challenge is checking to make sure it's done correctly.

Sperling: Lip-Bu, EDA360 was built around integration as a core tenet. Where are we now - is integration still a big issue?

Tan: I think complexity is increasing substantially. It's not just analog and digital IP blocks - it's the software stack as well. How do you put it together in an integrated form that drives power, performance, area, leakage, and cost? How do you integrate, optimize, and verify? That is why we articulated EDA360. It talks about how you do hardware/software co-design, and co-verification, in a very systematic, holistic way to drive performance requirements. Nobody can say they have all the solutions - we have to collaborate with different parties.

De Geus: We see a lot of problems multi-dimensionally. We're now touching a lot more physics, and here comes all this software. What happens if the software calls GPS 14 times per minute? We know exactly what happens - the battery is dead in 20 minutes. It's not hard to test but first you have to have the problem.

3   Power is a key IP concern for EDA customers.

Both the CEO panelists and the EDAC members identified power as the key IP concern for EDA customers. Here's why.

Tan: Power is a more and more critical issue, and one big concern is the data center, given all the cloud hosting data centers do. They are not looking for 10%, 30%, 40% -- they are looking for a 5-10X improvement in power. That means the methodology and the architecture of the design need innovation.

De Geus: First it was mobile, and then mobile exacerbated the data center issue. Underneath, power forces a radical look at many things. We are not only going to higher levels and optimizing, we are actually going back to lower levels too.

Rhines: At small dimensions, leakage has become significant, and now everybody has a problem and they all look to the EDA industry to solve it. The first round of solutions was to tweak the layout, then to tweak the RTL, and now we're tweaking the system design and changing the architecture.

Cheng: I've always had some problems with the words "low power." I want to think of it in terms of energy-efficient operation. This gives the designer a clearer parameter.

4.  The growth driver in EDA is change.

What technology challenge will spur the next growth spurt in EDA? When this question was posed to EDAC members, they split among the various options - mixed signal, HW/SW co-design, electronic system level (ESL), and IP reuse and integration.

De Geus: ESL had great potential, but how come it didn't grow so fast? Because it was really hard to get all the pieces to work together to come up with a result. And that's the nature of growth spurts in our industry. You need to get all the pieces together to finally reveal something, and then to establish that enough people are interested. You need something that really has impact and has enough customers.

Rhines: Growth only occurs in EDA when there is a methodology change. We had a decade of slow growth because there weren't that many big methodology changes. If you look at the figures, DFM [design for manufacturability] was 50% of the growth, ESL was 30%, the next biggest was power, and number four was formal. Everything else actually declined during the decade.

Tan: The semiconductor industry is facing a lot of challenges. I mentioned the power requirement in data centers. Another one is the move to multiple cores, which is being pushed by the systems guys. The Apples, Googles, and Facebooks are driving the requirements. Our tools have to be able to scale to meet these requirements. Let's work together as a team to help the industry move forward.

5.  The structure of the EDA industry won't change soon.

What will the EDA industry look like in 5 years? In response to the pre-panel question, EDAC members pointed to more startups and more consolidation.

Rhines: The more the structure of the industry changes, the more it remains the same. We grow the same number of new EDA companies every year, even though the number of VC-funded startups has declined to a very small number. Three big EDA companies have constituted 75% of the revenue for 40 years, even before Mentor, Daisy and Valid, and I'll bet this will be the case for another 30 years.

Tan: I'm very bullish about this [EDA] business. We're going to have a lot of problems to solve and we will continue to grow and encourage startups. Rather than waiting for somebody to consolidate us, if we continue to drive performance, we may be consolidating others.

De Geus: We can see the boundaries of our field [EDA] moving further down into physics and further into software. We're not going to take over mechanical [CAD] but we need to make sure we work with mechanical. We [Synopsys] acquired an optical company. These things at the boundary will continue.

6.  Most advanced designs will still be done in North America - for a while.

In response to one of the staged questions, both EDAC members and CEOs agreed that a majority of advanced designs during the next 5 years will be done in North America. It wasn't initially clear whether "design" indicated semiconductor or system design.

De Geus:  If we're talking chip design, the competence level in Asia-Pacific is coming up very rapidly. If we're talking about systems, other regions have tremendous capacity, and Europe is in that capability.

Segars: Where complex systems are designed right now is the U.S. I don't think 5 years is long enough to fundamentally change that.

Tan: In five years I agree [North America] but longer than that I'm not so sure. 10 years will be very different. 28nm designs are starting in China now and very shortly 20nm will be coming. Other countries are taking the lead now and in some ways the U.S. is falling behind. More and more great talent is educated in the U.S., but people are going back to their own countries. We have to focus on education and innovation and keep it here.

Conclusion - EDA Industry on the Move

In a way, I saved the best news for last. In his introductory remarks, Bob Gardner, EDA Consortium president, noted the recent EDA Consortium Market Statistics Survey that showed 18.1% year-over-year revenue growth in the third quarter of 2011. "This is really, really good for our business," he commented. It should be good for customers as well.

Richard Goering

 

Comments(1)

By Bob Gardner on March 14, 2012
Thanks for your positive and factual reporting.   This is a very refreshing change from much of what is usually put out these days.  
Professional journalism is GREAT!
Bob G.

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