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Customer, Partner DFM Concerns Spur New Methodologies

Comments(0)Filed under: Industry Insights, lithography, DFM, CMP, IP, Freescale, Design, GlobalFoundries, Cambridge, variability, 20nm, Samsung, manufacturing, foundries, LDE, LEA, design for manufacturability, layout-dependent effects, SPIE, hotspot, SPIE 2012, hot spot, Litho Electrical Analyzer, SPIE papers, Hurat, 28m, printability

Design for manufacturing (DFM) may not be as "hot" a topic as it was a few years ago - when there were many independent DFM companies - but foundries and chip design companies are in fact very concerned about DFM at 28nm and below. Some of those concerns have given rise to new technologies and methodologies that will be revealed next week (Feb. 12-16, 2012) in Cadence/customer co-authored papers at the SPIE Advanced Lithography conference in San Jose, California.

Philippe Hurat, product engineering director at Cadence, is the co-author of several "design side" DFM papers that will be given at SPIE. All describe engagements that Cadence has had with customers or partners. I talked to Hurat recently to learn more about these engagements and also about advanced-node DFM concerns in general. You can see a list of all Cadence co-authored SPIE 2012 papers (four of which concern computational lithography) in my previous blog post.

Customer Concerns

I asked Hurat what customers and partners are most concerned about at 28nm and below. "It depends on who they are," he replied. "Foundries are generally worried about printability, because a DRC-clean design that doesn't print still produces a bad yield. So most of the time, our work with foundries starts with printability or hotspot detection."

IC design houses, in contrast, are struggling with the integration of lithography or CMP checks into the design flow. A top priority, Hurat said, "is to make them more designer friendly. For the designer, having to run a DFM tool is a burden. So the easier you make it, the faster it is and the more automated, the less disruptive it is."

Moreover, he noted, variability has a big impact. At 28nm and even more so at 20nm, stress can cause significant timing variability, and layout dependent effects (LDE) become critical - that is, transistor performance will vary according to what is placed near it in the layout. Custom designers, library developers and chip designers must analyze and mitigate the impact on timing.

The Design House View

One of the SPIE DFM papers, In-design hierarchical DFM closure for DFM-clean IP, describes work that Cadence did with Freescale on manufacturability checks for litho and CMP at 28nm. "When you develop an IP block you want to make sure it is litho and CMP clean," Hurat said. "So we worked with Freescale to develop IP integration that fits their needs, and the paper will explain those requirements and how we achieved them for both litho and CMP." He explained that "CMP clean" is a tough requirement because CMP, unlike litho, has an effect over a large area that might go beyond the IP itself.

A second Cadence-Freescale paper is titled Analysis of layout-dependent context effects on timing and leakage at 28nm. This paper notes that at 28nm, the context - the layout surrounding a cell - impacts the timing and leakage of a cell due to stress and other LDE. It is one of several SPIE papers that describe the use of the Cadence Litho Electrical Analyzer (LEA) to analyze variability.

Another paper that discusses LEA and LDE is co-authored with Cambridge Silicon Radio and is titled Analysis, quantification, and mitigation of electrical variability due to layout-dependent effects in SoC designs. While the Freescale LDE paper is more focused on leakage and silicon results, the Cambridge Silicon Radio paper is primarily concerned with delay and mitigation strategies.

The Foundry View

Cadence and Samsung are presenting a paper titled In-design process hotspot repair by pattern matching.  This paper demonstrates a pattern-based approach for hotspot repair developed by Samsung that is much faster than traditional lithography simulation. Hurat noted that Cadence provided the entire flow, from pattern creation to pattern detection and hotspot fixing in place and route. (Note: The Cadence-Samsung partnership in DFM is further described in a Feb. 6 press release).

Finally, Cadence and GLOBALFOUNDRIES co-authored a paper titled Electrical design for manufacturability and layout-dependent variability hotspot detection flows at 28nm and 20nm. This paper is aimed at custom/analog design with the Cadence Virtuoso platform, and it shows that lithography as well as stress is a major source of LDE variability.

For more information about the Cadence co-authored papers, click here. A complete SPIE program is located here.

On the Manufacturing Side

In addition to these DFM papers, the above links will show you four papers that describe work that Cadence has done with partners on the "manufacturing" side of DFM (or, "computational lithography"). As Hurat noted, this is originally what SPIE was all about - design-side DFM was only added recently. Topics of the computational lithography papers include model calibration, source-mask optimization, self-aligned double patterning, and lithography target optimization.

If you're interested in DFM from any angle -- design or manufacturing, foundry or design house, custom/analog or digital -- SPIE 2012 is the place to be next week.

Richard Goering


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