RTL and gate-level simulation have been the workhorses of the IC verification environment for 25 years, and they're orders of magnitude faster than they used to be. But as chip complexity skyrockets and process nodes shrink, a continuous cry arises from verification teams - "make it faster, please!" As a recently published Cadence whitepaper shows, verification turn-around time does require faster simulation engines, but it involves much more than that.
The whitepaper is titled "Hardware Simulator Performance Scaling to Meet Advanced Node SoC Verification Requirements." It shows what is necessary to improve verification productivity for advanced-node chips, and notes recent improvements in the Incisive Enterprise Simulator that are aimed at performance scaling. The paper advocates a project-specific, "systematic" approach in which users first analyze the design and verification requirements to identify possible improvements. With significant testbench or design changes, a detailed profile is necessary to identify performance bottlenecks.
The whitepaper notes briefly that one way to increase verification turn-around time is to move to a higher level of abstraction, such as transaction-level modeling (TLM). There are also mentions of formal verification, acceleration, and emulation as productivity boosters. But for the most part the whitepaper focuses on how to get better and faster results with RTL and gate-level simulation.
Speeding Up the Core Simulator
What can be done to speed up the core simulator? Quite a lot, actually. The whitepaper describes some improvements made to the Incisive Enterprise Simulator during 2011, including:
- Assertion-based verification - A single finish for each cover property, optimizations focused on SystemVerilog assertions (SVA) sequence operators, and performance controls speed both subsystem and full SoC verification.
- Gate-level simulation - Complex expressions in timing outputs have been optimized.
- Coverage - Optimizations for mixed-language dumping, dynamic SystemVerilog objects, and toggle coverage contribute to runtime improvements; other optimizations minimize memory usage.
- Power-aware design - A native low-power solution has marginal overhead during both elaboration and run time.
The whitepaper shows how to configure a simulator for speed by arriving at the best tradeoff between performance and debug access. By default, Incisive runs in a fast mode with minimal debugging capability. Some debug options should be applied selectively rather than locally, or should not be used for regression.
The whitepaper also notes how CPU, cache, memory, storage, network, and operating system affect performance. (Note: I wrote recently about how Cadence IT experts are helping customers with these kinds of issues). The whitepaper recommends that project teams profile the simulation environment regularly, and shows how this is done.
Advanced Node Verification Requirements
While tuning the simulation engine can provide single-digit performance multiples, the whitepaper notes, advanced-node teams really need to focus on turn-around time at each stage of verification. Quite often the elaboration phase consumes significant time. Incremental elaboration is an Incisive feature that can help.
Turnaround time affects each verification stage for advanced node SoCs
The whitepaper also shows how dynamic reseeding saves regression time. It notes how multi-core operation speeds regression runs. It concludes with a discussion of the productivity gains provided by formal verification and hardware-based acceleration.
In short, this whitepaper is a great read for anyone who wants a more productive verification environment. Turn-around time, adequate coverage, and quality of results are the real goals - and "wall clock" time on a simulator is a means to get there, but is by no means the entire picture.
For further perspectives, see Adam Sherer's recent blog post.
Richard Goering